46 #define DDR_CTL_REG(d, i) (*(d->ddrctl + i))  macro
75 		DDR_CTL_REG(ddr_ctrl, i) = ddr_ctl_settings[i];  in ddr_writeregmap()
82 	return ((DDR_CTL_REG(ddr_ctrl, 0) >> DRAM_CLASS_OFFSET) & 0xF);  in ddr_getdramclass()
150 	DDR_CTL_REG(ddr_ctrl, 120) |= DISABLE_RD_INTERLEAVE;  in ddr_init()
151 	DDR_CTL_REG(ddr_ctrl, 21)  &= ~OPTIMAL_RMODW_EN;  in ddr_init()
152 	DDR_CTL_REG(ddr_ctrl, 170) |= WRLVL_EN | DFI_PHY_WRLELV_MODE;  in ddr_init()
153 	DDR_CTL_REG(ddr_ctrl, 181) |= DFI_PHY_RDLVL_MODE;  in ddr_init()
154 	DDR_CTL_REG(ddr_ctrl, 260) |= RDLVL_EN;  in ddr_init()
155 	DDR_CTL_REG(ddr_ctrl, 260) |= RDLVL_GATE_EN;  in ddr_init()
156 	DDR_CTL_REG(ddr_ctrl, 182) |= DFI_PHY_RDLVL_GATE_MODE;  in ddr_init()
159 		DDR_CTL_REG(ddr_ctrl, 184) |= VREF_EN;  in ddr_init()
162 	DDR_CTL_REG(ddr_ctrl, 136) |= LEVELING_OPERATION_COMPLETED;  in ddr_init()
163 	DDR_CTL_REG(ddr_ctrl, 136) |= MC_INIT_COMPLETE;  in ddr_init()
164 	DDR_CTL_REG(ddr_ctrl, 136) |= OUT_OF_RANGE | MULTIPLE_OUT_OF_RANGE;  in ddr_init()
169 	DDR_CTL_REG(ddr_ctrl, 209) = 0x0;  in ddr_init()
170 	DDR_CTL_REG(ddr_ctrl, 210) = ((uint32_t) end_addr_16Kblocks);  in ddr_init()
171 	DDR_CTL_REG(ddr_ctrl, 212) = 0x0;  in ddr_init()
172 	DDR_CTL_REG(ddr_ctrl, 214) = 0x0;  in ddr_init()
173 	DDR_CTL_REG(ddr_ctrl, 216) = 0x0;  in ddr_init()
174 	DDR_CTL_REG(ddr_ctrl, 224) |= AXI0_RANGE_PROT_BITS_0;  in ddr_init()
175 	DDR_CTL_REG(ddr_ctrl, 225) = 0xFFFFFFFF;  in ddr_init()
176 	DDR_CTL_REG(ddr_ctrl, 208) |= AXI0_ADDRESS_RANGE_ENABLE;  in ddr_init()
177 	DDR_CTL_REG(ddr_ctrl, 208) |= PORT_ADDR_PROTECTION_EN;  in ddr_init()
180 	DDR_CTL_REG(ddr_ctrl, 136) |= PORT_COMMAND_CHANNEL_ERROR;  in ddr_init()
182 	DDR_CTL_REG(ddr_ctrl, 0) |= 1;  in ddr_init()
184 	while ((DDR_CTL_REG(ddr_ctrl, 132) & MC_INIT_COMPLETE) != 0) {  in ddr_init()