Searched refs:DCKCFGR2_REG (Results 1 – 2 of 2) sorted by relevance
| /Zephyr-latest/include/zephyr/dt-bindings/clock/ |
| D | stm32f7_clock.h | 98 #define DCKCFGR2_REG 0x90 macro
102 #define USART1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 0, DCKCFGR2_REG)
103 #define USART2_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 2, DCKCFGR2_REG)
104 #define USART3_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 4, DCKCFGR2_REG)
105 #define USART4_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 6, DCKCFGR2_REG)
106 #define USART5_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 8, DCKCFGR2_REG)
107 #define USART6_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 10, DCKCFGR2_REG)
108 #define USART7_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 12, DCKCFGR2_REG)
109 #define USART8_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 14, DCKCFGR2_REG)
110 #define I2C1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 16, DCKCFGR2_REG)
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| D | stm32f410_clock.h | 11 #define DCKCFGR2_REG 0x94 macro
24 #define I2CFMP1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 22, DCKCFGR2_REG)
25 #define CK48M_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 27, DCKCFGR2_REG)
26 #define SDIO_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 28, DCKCFGR2_REG)
27 #define LPTIM1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 30, DCKCFGR2_REG)
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