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Searched refs:CPG_MOD (Results 1 – 10 of 10) sorted by relevance

/Zephyr-latest/dts/arm/renesas/rcar/gen3/
Dr8a77951.dtsi19 clocks = <&cpg CPG_MOD 916>,
24 clocks = <&cpg CPG_MOD 523>,
29 clocks = <&cpg CPG_MOD 206>,
34 clocks = <&cpg CPG_MOD 310>,
Drcar_gen3_cr7.dtsi51 clocks = <&cpg CPG_MOD 907>;
62 clocks = <&cpg CPG_MOD 906>;
87 clocks = <&cpg CPG_MOD 303>;
109 clocks = <&cpg CPG_MOD 929>;
122 clocks = <&cpg CPG_MOD 927>;
/Zephyr-latest/dts/arm/renesas/rcar/gen4/
Dr8a779f0.dtsi40 clocks = <&cpg CPG_MOD 915>;
54 clocks = <&cpg CPG_MOD 915>;
61 clocks = <&cpg CPG_MOD 702>, <&cpg CPG_CORE R8A779F0_CLK_S0D12_PER>;
67 clocks = <&cpg CPG_MOD 704>, <&cpg CPG_CORE R8A779F0_CLK_S0D12_PER>;
/Zephyr-latest/include/zephyr/dt-bindings/clock/
Drenesas_cpg_mssr.h11 #define CPG_MOD 1 /* Module Clock */ macro
/Zephyr-latest/dts/arm64/renesas/
Drcar_gen3_ca57.dtsi83 clocks = <&cpg CPG_MOD 907>;
92 clocks = <&cpg CPG_MOD 314>, <&cpg CPG_CORE R8A7795_CLK_SD0H>;
104 clocks = <&cpg CPG_MOD 312>, <&cpg CPG_CORE R8A7795_CLK_SD2H>;
118 clocks = <&cpg CPG_MOD 310>,
Dr8a779f0.dtsi97 clocks = <&cpg CPG_MOD 706>, <&cpg CPG_CORE R8A779F0_CLK_SD0H>;
114 clocks = <&cpg CPG_MOD 514>, <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>;
/Zephyr-latest/drivers/clock_control/
Dclock_control_r8a779f0_cpg_mssr.c151 if (clk->domain == CPG_MOD) { in r8a779f0_cpg_mssr_start_stop()
272 .cmn.clk_info_table[CPG_MOD] = mod_props, \
273 .cmn.clk_info_table_size[CPG_MOD] = ARRAY_SIZE(mod_props), \
Dclock_control_r8a7795_cpg_mssr.c157 if (clk->domain == CPG_MOD) { in r8a7795_cpg_mssr_start_stop()
281 .cmn.clk_info_table[CPG_MOD] = mod_props, \
282 .cmn.clk_info_table_size[CPG_MOD] = ARRAY_SIZE(mod_props), \
Dclock_control_renesas_cpg_mssr.h66 .domain = CPG_MOD, \
Dclock_control_renesas_cpg_mssr.c97 if (clk_info->domain == CPG_MOD) { in rcar_cpg_get_divider()
283 if (clk_info->domain == CPG_MOD) { in rcar_cpg_set_rate()