| /Zephyr-latest/arch/arm/core/cortex_m/ |
| D | fpu.c | 22 uint32_t CONTROL = __get_CONTROL(); in z_arm_save_fp_context() local
24 if (CONTROL & CONTROL_FPCA_Msk) { in z_arm_save_fp_context()
35 __set_CONTROL(CONTROL & ~CONTROL_FPCA_Msk); in z_arm_save_fp_context()
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| D | reset.S | 74 msr CONTROL, r0
191 mrs r0, CONTROL
194 msr CONTROL, r0
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| D | swap_helper.S | 229 mrs r3, CONTROL
233 msr CONTROL, r3
286 mrs r3, CONTROL
288 msr CONTROL, r3
303 mrs r3, CONTROL
306 msr CONTROL, r3
403 mrs r2, CONTROL
550 msr CONTROL, r2
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| /Zephyr-latest/drivers/peci/ |
| D | peci_mchp_xec.c | 162 regs->CONTROL = MCHP_PECI_CTRL_PD; in peci_xec_configure()
171 regs->CONTROL &= ~MCHP_PECI_CTRL_PD; in peci_xec_configure()
193 regs->CONTROL |= MCHP_PECI_CTRL_PD; in peci_xec_disable()
203 regs->CONTROL &= ~MCHP_PECI_CTRL_PD; in peci_xec_enable()
221 regs->CONTROL = MCHP_PECI_CTRL_PD | MCHP_PECI_CTRL_RST; in peci_xec_bus_recovery()
229 regs->CONTROL &= ~MCHP_PECI_CTRL_RST; in peci_xec_bus_recovery()
234 regs->CONTROL |= MCHP_PECI_CTRL_FRST; in peci_xec_bus_recovery()
255 regs->CONTROL &= ~MCHP_PECI_CTRL_FRST; in peci_xec_write()
278 regs->CONTROL |= MCHP_PECI_CTRL_TXEN; in peci_xec_write()
459 regs->CONTROL &= ~MCHP_PECI_CTRL_PD; in peci_xec_pm_action()
[all …]
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| D | peci_ite_it8xxx2.c | 69 #define CONTROL BIT(2) macro
201 peci_regs->HOCTLR |= (FIFOCLR|FCSERR_ABT|PECIHEN|CONTROL); in peci_it8xxx2_enable()
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| /Zephyr-latest/drivers/sensor/microchip/mchp_tach_xec/ |
| D | tach_mchp_xec.c | 65 tach->CONTROL >> MCHP_TACH_CTRL_COUNTER_POS; in tach_xec_sample_fetch()
139 tach->CONTROL |= MCHP_TACH_CTRL_EN; in tach_xec_pm_action()
144 if (tach->CONTROL & MCHP_TACH_CTRL_EN) { in tach_xec_pm_action()
146 data->control = tach->CONTROL; in tach_xec_pm_action()
147 tach->CONTROL &= (~MCHP_TACH_CTRL_EN); in tach_xec_pm_action()
172 tach->CONTROL = MCHP_TACH_CTRL_READ_MODE_100K_CLOCK | in tach_xec_init()
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| /Zephyr-latest/arch/arm/core/ |
| D | userspace.S | 260 mrs r3, CONTROL
272 mrs ip, CONTROL
278 msr CONTROL, ip
549 mrs r2, CONTROL
551 msr CONTROL, r2
564 mrs ip, CONTROL
566 msr CONTROL, ip
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| /Zephyr-latest/soc/microchip/mec/mec172x/ |
| D | device_power.c | 255 adc0->CONTROL &= ~(MCHP_ADC_CTRL_ACTV); in deep_sleep_save_blocks()
261 ds_ctx.peci_info.peci_ctrl = peci->CONTROL; in deep_sleep_save_blocks()
314 adc0->CONTROL |= MCHP_ADC_CTRL_ACTV; in deep_sleep_restore_blocks()
321 peci->CONTROL = ds_ctx.peci_info.peci_ctrl; in deep_sleep_restore_blocks()
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| /Zephyr-latest/soc/microchip/mec/common/reg/ |
| D | mec_tach.h | 85 volatile uint32_t CONTROL; member
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| D | mec_adc.h | 161 volatile uint32_t CONTROL; member
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| D | mec_peci.h | 122 volatile uint8_t CONTROL; member
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| /Zephyr-latest/drivers/entropy/ |
| D | entropy_gecko_trng.c | 139 TRNG0->CONTROL = TRNG_CONTROL_ENABLE; in entropy_gecko_trng_init()
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| /Zephyr-latest/drivers/crypto/ |
| D | crypto_si32.c | 130 __ASSERT(SI32_AES_0->CONTROL.RESET == 0, "Reset done"); in crypto_si32_init()
646 __ASSERT(SI32_AES_0->CONTROL.ERRIEN == 1, "a. ERRIEN set to 1."); in crypto_si32_aes_ecb_op()
804 __ASSERT(SI32_AES_0->CONTROL.ERRIEN == 1, "a. ERRIEN set to 1."); in crypto_si32_aes_cbc_op()
946 __ASSERT(SI32_AES_0->CONTROL.ERRIEN == 1, "a. ERRIEN set to 1."); in crypto_si32_aes_ctr_op()
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| /Zephyr-latest/modules/ |
| D | Kconfig.renesas_fsp | 219 Enable RZ FSP CLOCK CONTROL driver
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| /Zephyr-latest/boards/pine64/pinetime_devkit0/doc/ |
| D | index.rst | 82 | P0.24 | 3V3 POWER CONTROL | OUT |
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| /Zephyr-latest/scripts/ci/ |
| D | pylintrc | 32 [MESSAGES CONTROL]
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| /Zephyr-latest/drivers/usb/device/ |
| D | usb_dc_kinetis.c | 243 USB0->CONTROL = USB_CONTROL_DPPULLUPNONOTG_MASK; in usb_dc_attach()
253 USB0->CONTROL &= ~USB_CONTROL_DPPULLUPNONOTG_MASK; in usb_dc_detach()
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| /Zephyr-latest/drivers/usb/udc/ |
| D | udc_kinetis.c | 947 base->CONTROL = USB_CONTROL_DPPULLUPNONOTG_MASK; in usbfsotg_enable()
959 base->CONTROL &= ~USB_CONTROL_DPPULLUPNONOTG_MASK; in usbfsotg_disable()
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| /Zephyr-latest/drivers/flash/ |
| D | flash_cadence_nand_ll.c | 379 sys_set_bit(CNF_DI(base_address, CONTROL), CNF_DI_PAR_EN); in cdns_nand_init()
385 sys_set_bit(CNF_DI(base_address, CONTROL), CNF_DI_CRC_EN); in cdns_nand_init()
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| /Zephyr-latest/boards/nordic/nrf7002dk/doc/ |
| D | index.rst | 153 * IOVDD CONTROL = **P0.31**
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| /Zephyr-latest/doc/hardware/arch/ |
| D | arm_cortex_m.rst | 385 * modify CONTROL register to switch to privileged mode
390 user's original PSP and PSPLIM and switch the CONTROL register back to unprivileged mode
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