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Searched refs:CONFIG_NUM_IRQS (Results 1 – 25 of 41) sorted by relevance

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/Zephyr-latest/drivers/interrupt_controller/
Dintc_vim.c36 return CONFIG_NUM_IRQS + 1; in z_vim_irq_get_active()
46 return (CONFIG_NUM_IRQS + 1); in z_vim_irq_get_active()
68 if (irq > CONFIG_NUM_IRQS || prio > VIM_PRI_INT_MAX || in z_vim_irq_priority_set()
95 if (irq > CONFIG_NUM_IRQS) { in z_vim_irq_enable()
110 if (irq > CONFIG_NUM_IRQS) { in z_vim_irq_disable()
125 if (irq > CONFIG_NUM_IRQS) { in z_vim_irq_is_enabled()
142 if (irq > CONFIG_NUM_IRQS) { in z_vim_arm_enter_irq()
Dintc_arcv2_irq_unit.c34 BUILD_ASSERT(CONFIG_NUM_IRQS > ARC_CONNECT_IDU_IRQ_START); in arc_shared_intc_init()
40 for (uint32_t i = 0; i < (CONFIG_NUM_IRQS - ARC_CONNECT_IDU_IRQ_START); i++) { in arc_shared_intc_init()
70 for (uint32_t i = 0; i < (CONFIG_NUM_IRQS - ARC_CONNECT_IDU_IRQ_START); i++) { in arc_shared_intc_update_post_smp()
129 for (uint32_t irq = ARC_CONNECT_IDU_IRQ_START; irq < CONFIG_NUM_IRQS; irq++) { in arc_core_private_intc_init()
133 for (uint32_t irq = CONFIG_GEN_IRQ_START_VECTOR; irq < CONFIG_NUM_IRQS; irq++) { in arc_core_private_intc_init()
Dintc_ite_it8xxx2_v2.c82 if (irq > CONFIG_NUM_IRQS) { in ite_intc_isr_clear()
96 if (irq > CONFIG_NUM_IRQS) { in ite_intc_irq_enable()
115 if (irq > CONFIG_NUM_IRQS) { in ite_intc_irq_disable()
139 if (irq > CONFIG_NUM_IRQS) { in ite_intc_irq_polarity_set()
167 if (irq > CONFIG_NUM_IRQS) { in ite_intc_irq_is_enable()
Dintc_ite_it8xxx2.c104 if (irq > CONFIG_NUM_IRQS) { in ite_intc_isr_clear()
118 if (irq > CONFIG_NUM_IRQS) { in ite_intc_irq_enable()
137 if (irq > CONFIG_NUM_IRQS) { in ite_intc_irq_disable()
160 if ((irq > CONFIG_NUM_IRQS) || ((flags&IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH)) { in ite_intc_irq_polarity_set()
184 if (irq > CONFIG_NUM_IRQS) { in ite_intc_irq_is_enable()
/Zephyr-latest/include/zephyr/arch/xtensa/
Dirq.h73 #define CONFIG_NUM_IRQS (XCHAL_NUM_INTERRUPTS +\ macro
78 #define CONFIG_NUM_IRQS (XCHAL_NUM_INTERRUPTS +\ macro
83 #define CONFIG_NUM_IRQS XCHAL_NUM_INTERRUPTS macro
104 #define CONFIG_NUM_IRQS XCHAL_NUM_INTERRUPTS macro
/Zephyr-latest/tests/kernel/interrupt/src/
Dnested_irq.c76 #define IRQ0_LINE (CONFIG_NUM_IRQS - 1)
77 #define IRQ1_LINE (CONFIG_NUM_IRQS - 2)
145 irq_line_0 = get_available_nvic_line(CONFIG_NUM_IRQS); in ZTEST()
Ddynamic_isr.c48 for (i = 0; i < (CONFIG_NUM_IRQS - CONFIG_GEN_IRQ_START_VECTOR); i++) { in ZTEST()
/Zephyr-latest/tests/arch/arm/arm_sw_vector_relay/src/
Darm_sw_vector_relay.c29 for (int i = 2; i < 16 + CONFIG_NUM_IRQS; i++) { in ZTEST()
43 uint32_t mask = MAX(128, Z_POW2_CEIL(4 * (16 + CONFIG_NUM_IRQS))) - 1; in ZTEST()
/Zephyr-latest/tests/arch/arm/arm_irq_vector_table/
Dprj.conf3 CONFIG_NUM_IRQS=3
/Zephyr-latest/arch/arm/core/cortex_m/
Dirq_init.c34 for (; irq < CONFIG_NUM_IRQS; irq++) {
Dirq_relay.S73 .rept CONFIG_NUM_IRQS
Drelay_vector_table.ld28 . = ALIGN( 1 << LOG2CEIL(4 * (16 + CONFIG_NUM_IRQS)) );
/Zephyr-latest/soc/renesas/rz/rzt2l/
Dsoc.h34 SHARED_PERIPHERAL_INTERRUPTS_MAX_ENTRIES = CONFIG_NUM_IRQS
/Zephyr-latest/soc/renesas/rz/rzn2l/
Dsoc.h34 SHARED_PERIPHERAL_INTERRUPTS_MAX_ENTRIES = CONFIG_NUM_IRQS
/Zephyr-latest/tests/arch/arm/arm_custom_interrupt/src/
Darm_custom_interrupt.c32 for (; irq < CONFIG_NUM_IRQS; irq++) { in z_soc_irq_init()
130 for (i = CONFIG_NUM_IRQS - 1; i >= 0; i--) { in ZTEST()
/Zephyr-latest/tests/arch/arm/arm_irq_advanced_features/src/
Darm_dynamic_direct_interrupts.c13 #define DIRECT_ISR_OFFSET (CONFIG_NUM_IRQS - 1)
Darm_zero_latency_irqs.c38 for (i = CONFIG_NUM_IRQS - 1; i >= 0; i--) { in ZTEST()
Darm_irq_target_state.c23 for (i = CONFIG_NUM_IRQS - 1; i >= 0; i--) { in ZTEST()
/Zephyr-latest/tests/kernel/gen_isr_table/src/
Dmain.c106 #define TEST_NUM_IRQS CONFIG_NUM_IRQS
110 (CONFIG_NUM_IRQS - TEST_NUM_IRQS))
411 TC_PRINT("IRQ configuration (total lines %d):\n", CONFIG_NUM_IRQS); in gen_isr_table_setup()
/Zephyr-latest/arch/arc/core/
Dirq_offload.c23 #define IRQ_OFFLOAD_LINE (CONFIG_NUM_IRQS - 3)
/Zephyr-latest/arch/common/
Disr_tables.c76 LISTIFY(CONFIG_NUM_IRQS, BUILD_VECTOR, (;)); in _irq_vector_table()
/Zephyr-latest/modules/cmsis/
Dcmsis_core_m_defaults.h46 Max_IRQn = CONFIG_NUM_IRQS,
/Zephyr-latest/tests/arch/arm/arm_no_multithreading/src/
Dmain.c93 for (i = CONFIG_NUM_IRQS - 1; i >= 0; i--) { in test_main()
/Zephyr-latest/arch/arm/core/cortex_a_r/
Disr_wrapper.S202 mov r1, #CONFIG_NUM_IRQS
303 mov r1, #CONFIG_NUM_IRQS
/Zephyr-latest/include/zephyr/dt-bindings/interrupt-controller/
Dite-intc.h172 #define IT8XXX2_IRQ_COUNT (CONFIG_NUM_IRQS + 1)

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