Searched refs:CLOCK_DIVIDER (Results 1 – 8 of 8) sorted by relevance
| /Zephyr-latest/soc/nxp/kinetis/k2x/ |
| D | soc.c | 33 #define CLOCK_DIVIDER(clk) \ macro
67 .clkdiv1 = SIM_CLKDIV1_OUTDIV1(CLOCK_DIVIDER(core_clk)) |
68 SIM_CLKDIV1_OUTDIV2(CLOCK_DIVIDER(bus_clk)) |
69 SIM_CLKDIV1_OUTDIV3(CLOCK_DIVIDER(flexbus_clk)) |
70 SIM_CLKDIV1_OUTDIV4(CLOCK_DIVIDER(flash_clk)),
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| /Zephyr-latest/soc/nxp/kinetis/kv5x/ |
| D | soc.c | 25 #define CLOCK_DIVIDER(clk) \ macro
60 .clkdiv1 = SIM_CLKDIV1_OUTDIV1(CLOCK_DIVIDER(core_clk)) |
61 SIM_CLKDIV1_OUTDIV2(CLOCK_DIVIDER(bus_clk)) |
62 SIM_CLKDIV1_OUTDIV3(CLOCK_DIVIDER(flexbus_clk)) |
63 SIM_CLKDIV1_OUTDIV4(CLOCK_DIVIDER(flash_clk)),
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| /Zephyr-latest/soc/nxp/kinetis/k8x/ |
| D | soc.c | 28 #define CLOCK_DIVIDER(clk) \ macro
63 .clkdiv1 = SIM_CLKDIV1_OUTDIV1(CLOCK_DIVIDER(core_clk)) |
64 SIM_CLKDIV1_OUTDIV2(CLOCK_DIVIDER(bus_clk)) |
65 SIM_CLKDIV1_OUTDIV3(CLOCK_DIVIDER(flexbus_clk)) |
66 SIM_CLKDIV1_OUTDIV4(CLOCK_DIVIDER(flash_clk)),
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| /Zephyr-latest/soc/nxp/kinetis/k6x/ |
| D | soc.c | 35 #define CLOCK_DIVIDER(clk) \ macro
70 .clkdiv1 = SIM_CLKDIV1_OUTDIV1(CLOCK_DIVIDER(core_clk)) |
71 SIM_CLKDIV1_OUTDIV2(CLOCK_DIVIDER(bus_clk)) |
72 SIM_CLKDIV1_OUTDIV3(CLOCK_DIVIDER(flexbus_clk)) |
73 SIM_CLKDIV1_OUTDIV4(CLOCK_DIVIDER(flash_clk)),
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| /Zephyr-latest/soc/nxp/kinetis/kwx/ |
| D | soc_kw2xd.c | 32 #define CLOCK_DIVIDER(clk) \ macro
67 .clkdiv1 = SIM_CLKDIV1_OUTDIV1(CLOCK_DIVIDER(core_clk)) |
68 SIM_CLKDIV1_OUTDIV2(CLOCK_DIVIDER(bus_clk)) |
69 SIM_CLKDIV1_OUTDIV4(CLOCK_DIVIDER(flash_clk)),
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| D | soc_kw4xz.c | 21 #define CLOCK_DIVIDER(clk) \ macro
40 .clkdiv1 = SIM_CLKDIV1_OUTDIV1(CLOCK_DIVIDER(core_clk)) |
41 SIM_CLKDIV1_OUTDIV4(CLOCK_DIVIDER(flash_clk)),
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| /Zephyr-latest/soc/nxp/kinetis/kl2x/ |
| D | soc.c | 20 #define CLOCK_DIVIDER(clk) \ macro
39 .clkdiv1 = SIM_CLKDIV1_OUTDIV1(CLOCK_DIVIDER(core_clk)) | in clock_init()
40 SIM_CLKDIV1_OUTDIV4(CLOCK_DIVIDER(flash_clk)), in clock_init()
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| /Zephyr-latest/soc/nxp/mcx/mcxc/ |
| D | soc.c | 30 #define CLOCK_DIVIDER(clk) DT_PROP_OR(CLOCK_NODEID(clk), clock_div, 1) - 1 macro
65 .clkdiv1 = SIM_CLKDIV1_OUTDIV1(CLOCK_DIVIDER(core_clk)) |
66 SIM_CLKDIV1_OUTDIV4(CLOCK_DIVIDER(flash_clk)),
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