| /Zephyr-latest/soc/xlnx/zynq7000/xc7zxxx/ |
| D | Kconfig.soc | 14 SoC series (dual core ARM Cortex-A9).
20 2 ARM Cortex-A9 cores up to 866 MHz, Artix-7 programmable logic,
27 2 ARM Cortex-A9 cores up to 866 MHz, Artix-7 programmable logic,
35 2 ARM Cortex-A9 cores up to 866 MHz, Artix-7 programmable logic,
42 2 ARM Cortex-A9 cores up to 1 GHz, Kintex-7 programmable logic,
50 2 ARM Cortex-A9 cores up to 1 GHz, Kintex-7 programmable logic,
58 2 ARM Cortex-A9 cores up to 1 GHz, Kintex-7 programmable logic,
66 2 ARM Cortex-A9 cores up to 1 GHz, Kintex-7 programmable logic,
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| /Zephyr-latest/soc/xlnx/zynq7000/xc7zxxxs/ |
| D | Kconfig.soc | 14 SoC series (single core ARM Cortex-A9).
20 1 ARM Cortex-A9 core up to 766 MHz, Artix-7 programmable logic,
27 1 ARM Cortex-A9 core up to 766 MHz, Artix-7 programmable logic,
35 1 ARM Cortex-A9 core up to 766 MHz, Artix-7 programmable logic,
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| /Zephyr-latest/scripts/coredump/gdbstubs/arch/ |
| D | xtensa.py | 293 A9 = 98 variable in GdbRegDef_Sample_Controller.RegNum
327 A9 = 166 variable in GdbRegDef_ESP32.RegNum
359 A9 = 164 variable in GdbRegDef_ESP32S2.RegNum
389 A9 = 221 variable in GdbRegDef_ESP32S3.RegNum
430 A9 = 167 variable in GdbRegDef_Intel_Adsp_CAVS_Zephyr.RegNum
470 A9 = 265 variable in GdbRegDef_Intel_Adsp_CAVS_XCC.RegNum
505 A9 = 114 variable in GdbRegDef_DC233C.RegNum
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| /Zephyr-latest/boards/udoo/udoo_neo_full/doc/ |
| D | index.rst | 8 composed of one ARM |reg| Cortex-A9 core running up to 1 GHz and one Cortex-M4
11 will also communicate with the Cortex-A9 core (running Linux) via OpenAMP.
16 - MCIMX6X MCU with a single Cortex-A9 (1 GHz) core and single Cortex-M4 (227 MHz) core
28 - A9 Boot Devices
64 - 32x GPIO (A9)
152 PLL settings for M4 core are set via code running on the A9 core.
158 remaining are used by the A9 core or not used.
164 at power-on-reset. Therefore it needs to be started by the A9 core.
165 The A9 core is responsible to load the M4 binary application into the RAM,
167 the M4 out of reset. The A9 can perform these steps at the bootloader level
[all …]
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| /Zephyr-latest/boards/qemu/cortex_a9/ |
| D | Kconfig | 2 # Kconfig - Cortex-A9 QEMU Emulation
|
| D | Kconfig.qemu_cortex_a9 | 2 # Kconfig - Cortex-A9 QEMU Emulation
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| D | Kconfig.defconfig | 2 # Kconfig - Cortex-A9 (Zynq-7000) QEMU Emulation
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| D | qemu_cortex_a9.dts | 12 model = "QEMU Cortex-A9";
|
| /Zephyr-latest/boards/sparkfun/pro_micro_rp2040/ |
| D | sparkfun_pro_micro_connector.dtsi | 23 , <9 0 &gpio0 9 0> /* D9/A9 */
|
| /Zephyr-latest/boards/adafruit/kb2040/ |
| D | sparkfun_pro_micro_connector.dtsi | 23 , <9 0 &gpio0 9 0> /* D9/A9 */
|
| /Zephyr-latest/doc/ |
| D | substitutions.txt | 12 .. |copy| unicode:: U+000A9 .. COPYRIGHT SIGN
|
| /Zephyr-latest/drivers/timer/ |
| D | Kconfig.arm_arch | 23 ARM Cortex-A9 processors Software Developers Errata Notice, ARM
|
| /Zephyr-latest/samples/tfm_integration/psa_crypto/ |
| D | README.rst | 275 00000060 A7 A8 A9 AA AB AC AD AE AF B0 B1 B2 B3 B4 B5 B6 ................
290 00000150 2A 48 82 FA 9D 48 23 EF B1 66 A9 EF 6A 6E 4A A3 *H...H#..f..jnJ.
294 00000190 A9 22 AD 3A 00 01 25 01 77 77 77 77 2E 74 72 75 .".:..%.wwww.tru
355 000000E0 80 ED 7E 9D 0A 21 09 9C 9C 55 A9 14 AF A2 66 65 ..~..!...U....fe
356 000000F0 DE 8D BE C2 8B 31 B8 ED 06 AE A9 0B 7E 62 75 87 .....1......~bu.
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| /Zephyr-latest/boards/digilent/zybo/doc/ |
| D | index.rst | 12 dual-core ARM Cortex-A9 processor with Xilinx 7-series Field Programmable Gate Array (FPGA) logic.
|
| /Zephyr-latest/arch/arm/core/cortex_a_r/ |
| D | Kconfig | 21 This option signifies the use of a Cortex-A9 CPU.
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| /Zephyr-latest/boards/intel/socfpga_std/cyclonev_socdk/doc/ |
| D | index.rst | 137 This system is composed by the HPS, ARM Cortex-A9. In this example the UART, timer,
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| /Zephyr-latest/boards/snps/hsdk/doc/ |
| D | index.rst | 134 | A9 | n.c. | n.c. | n.c. | n.c. | n.c. | n.c. |
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| /Zephyr-latest/boards/snps/hsdk4xd/doc/ |
| D | index.rst | 131 | A9 | n.c. | n.c. | n.c. | n.c. | n.c. | n.c. |
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| /Zephyr-latest/doc/releases/ |
| D | release-notes-3.2.rst | 1935 * :github:`49814` - Cortex-A9 fails to build cmsis due to missing core_ca.h
|
