Searched refs:tx_desc (Results 1 – 5 of 5) sorted by relevance
245 struct eth_cyclonev_dma_desc *tx_desc; in eth_cyclonev_setup_txdesc() local249 tx_desc = &p->tx_desc_ring[i]; in eth_cyclonev_setup_txdesc()250 tx_desc->buffer1_addr = (uint32_t)&p->tx_buf[i * ETH_BUFFER_SIZE]; in eth_cyclonev_setup_txdesc()251 tx_desc->buffer2_next_desc_addr = (uint32_t)&p->tx_desc_ring[i + 1]; in eth_cyclonev_setup_txdesc()252 tx_desc->status = 0; in eth_cyclonev_setup_txdesc()253 tx_desc->control_buffer_size = 0; in eth_cyclonev_setup_txdesc()256 tx_desc->buffer2_next_desc_addr = (uint32_t)&p->tx_desc_ring[0]; in eth_cyclonev_setup_txdesc()403 struct eth_cyclonev_dma_desc *tx_desc; in eth_cyclonev_send() local419 tx_desc = &p->tx_desc_ring[p->tx_current_desc_number]; in eth_cyclonev_send()422 if (tx_desc->status & ETH_DMATXDESC_OWN) { in eth_cyclonev_send()[all …]
112 struct vring_desc *tx_desc = &q->tx.vring.desc[q->tx.desc_head]; in eth_ivshmem_queue_tx_get_buff() local114 tx_desc->addr = q->vring_header_size + head; in eth_ivshmem_queue_tx_get_buff()115 tx_desc->len = len; in eth_ivshmem_queue_tx_get_buff()116 tx_desc->flags = 0; in eth_ivshmem_queue_tx_get_buff()117 VRING_FLUSH(*tx_desc); in eth_ivshmem_queue_tx_get_buff()
704 struct gmac_desc *tx_desc; in tx_completed()719 tx_desc = &tx_desc_list->buf[tx_desc_list->tail]; in tx_completed()728 if (tx_desc->w1 & GMAC_TXW1_LASTBUFFER) { in tx_completed()1409 struct gmac_desc *tx_desc; in eth_tx() local1476 tx_desc = &tx_desc_list->buf[tx_desc_list->head]; in eth_tx()1479 tx_desc->w0 = (uint32_t)frag_data; in eth_tx()1484 tx_desc->w1 = (frag_len & GMAC_TXW1_LEN) in eth_tx()1488 | (tx_desc == tx_first_desc ? GMAC_TXW1_USED : 0); in eth_tx()
737 struct xgmac_dma_tx_desc *tx_desc; in eth_dwc_xgmac_tx_irq_work() local746 tx_desc = (struct xgmac_dma_tx_desc *)(fisrt_tx_desc + desc_idx); in eth_dwc_xgmac_tx_irq_work()747 arch_dcache_invd_range(tx_desc, sizeof(tx_desc)); in eth_dwc_xgmac_tx_irq_work()748 if (!(tx_desc->tdes3 & XGMAC_TDES3_OWN)) { in eth_dwc_xgmac_tx_irq_work()750 if (tx_desc->tdes3 & XGMAC_TDES3_LD) { in eth_dwc_xgmac_tx_irq_work()761 tx_desc->tdes0 = 0u; in eth_dwc_xgmac_tx_irq_work()762 tx_desc->tdes1 = 0u; in eth_dwc_xgmac_tx_irq_work()763 tx_desc->tdes2 = 0u; in eth_dwc_xgmac_tx_irq_work()764 tx_desc->tdes3 = 0u; in eth_dwc_xgmac_tx_irq_work()765 arch_dcache_flush_range(tx_desc, sizeof(tx_desc)); in eth_dwc_xgmac_tx_irq_work()[all …]
457 struct xgmac_dma_tx_desc *tx_desc; member
