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Searched refs:src_clk (Results 1 – 7 of 7) sorted by relevance

/Zephyr-Core-3.7.0/drivers/clock_control/
Dclock_stm32_ll_h5.c120 static int enabled_clock(uint32_t src_clk) in enabled_clock() argument
122 if ((src_clk == STM32_SRC_SYSCLK) || in enabled_clock()
123 ((src_clk == STM32_SRC_HSE) && IS_ENABLED(STM32_HSE_ENABLED)) || in enabled_clock()
124 ((src_clk == STM32_SRC_HSI) && IS_ENABLED(STM32_HSI_ENABLED)) || in enabled_clock()
125 ((src_clk == STM32_SRC_HSI48) && IS_ENABLED(STM32_HSI48_ENABLED)) || in enabled_clock()
126 ((src_clk == STM32_SRC_LSE) && IS_ENABLED(STM32_LSE_ENABLED)) || in enabled_clock()
127 ((src_clk == STM32_SRC_LSI) && IS_ENABLED(STM32_LSI_ENABLED)) || in enabled_clock()
128 ((src_clk == STM32_SRC_CSI) && IS_ENABLED(STM32_CSI_ENABLED)) || in enabled_clock()
129 ((src_clk == STM32_SRC_PLL1_P) && IS_ENABLED(STM32_PLL_P_ENABLED)) || in enabled_clock()
130 ((src_clk == STM32_SRC_PLL1_Q) && IS_ENABLED(STM32_PLL_Q_ENABLED)) || in enabled_clock()
[all …]
Dclock_stm32_ll_u5.c124 static int enabled_clock(uint32_t src_clk) in enabled_clock() argument
126 if ((src_clk == STM32_SRC_SYSCLK) || in enabled_clock()
127 ((src_clk == STM32_SRC_HSE) && IS_ENABLED(STM32_HSE_ENABLED)) || in enabled_clock()
128 ((src_clk == STM32_SRC_HSI16) && IS_ENABLED(STM32_HSI_ENABLED)) || in enabled_clock()
129 ((src_clk == STM32_SRC_HSI48) && IS_ENABLED(STM32_HSI48_ENABLED)) || in enabled_clock()
130 ((src_clk == STM32_SRC_LSE) && IS_ENABLED(STM32_LSE_ENABLED)) || in enabled_clock()
131 ((src_clk == STM32_SRC_LSI) && IS_ENABLED(STM32_LSI_ENABLED)) || in enabled_clock()
132 ((src_clk == STM32_SRC_MSIS) && IS_ENABLED(STM32_MSIS_ENABLED)) || in enabled_clock()
133 ((src_clk == STM32_SRC_MSIK) && IS_ENABLED(STM32_MSIK_ENABLED)) || in enabled_clock()
134 ((src_clk == STM32_SRC_PLL1_P) && IS_ENABLED(STM32_PLL_P_ENABLED)) || in enabled_clock()
[all …]
Dclock_stm32_ll_h7.c362 static int enabled_clock(uint32_t src_clk) argument
365 if ((src_clk == STM32_SRC_SYSCLK) ||
366 ((src_clk == STM32_SRC_CKPER) && IS_ENABLED(STM32_CKPER_ENABLED)) ||
367 ((src_clk == STM32_SRC_HSE) && IS_ENABLED(STM32_HSE_ENABLED)) ||
368 ((src_clk == STM32_SRC_HSI_KER) && IS_ENABLED(STM32_HSI_ENABLED)) ||
369 ((src_clk == STM32_SRC_CSI_KER) && IS_ENABLED(STM32_CSI_ENABLED)) ||
370 ((src_clk == STM32_SRC_HSI48) && IS_ENABLED(STM32_HSI48_ENABLED)) ||
371 ((src_clk == STM32_SRC_LSE) && IS_ENABLED(STM32_LSE_ENABLED)) ||
372 ((src_clk == STM32_SRC_LSI) && IS_ENABLED(STM32_LSI_ENABLED)) ||
373 ((src_clk == STM32_SRC_PLL1_P) && IS_ENABLED(STM32_PLL_P_ENABLED)) ||
[all …]
Dclock_stm32_ll_wba.c45 static int enabled_clock(uint32_t src_clk) in enabled_clock() argument
47 if ((src_clk == STM32_SRC_SYSCLK) || in enabled_clock()
48 ((src_clk == STM32_SRC_HSE) && IS_ENABLED(STM32_HSE_ENABLED)) || in enabled_clock()
49 ((src_clk == STM32_SRC_HSI16) && IS_ENABLED(STM32_HSI_ENABLED)) || in enabled_clock()
50 ((src_clk == STM32_SRC_LSE) && IS_ENABLED(STM32_LSE_ENABLED)) || in enabled_clock()
51 ((src_clk == STM32_SRC_LSI) && IS_ENABLED(STM32_LSI_ENABLED)) || in enabled_clock()
52 ((src_clk == STM32_SRC_PLL1_P) && IS_ENABLED(STM32_PLL_P_ENABLED)) || in enabled_clock()
53 ((src_clk == STM32_SRC_PLL1_Q) && IS_ENABLED(STM32_PLL_Q_ENABLED)) || in enabled_clock()
54 ((src_clk == STM32_SRC_PLL1_R) && IS_ENABLED(STM32_PLL_R_ENABLED))) { in enabled_clock()
Dclock_stm32_ll_common.c117 static int enabled_clock(uint32_t src_clk) in enabled_clock() argument
121 switch (src_clk) { in enabled_clock()
/Zephyr-Core-3.7.0/drivers/serial/
Duart_npcx.c120 static int uart_set_npcx_baud_rate(struct uart_reg *const inst, int baud_rate, int src_clk) in uart_set_npcx_baud_rate() argument
128 if (src_clk == MHZ(15)) { in uart_set_npcx_baud_rate()
131 } else if (src_clk == MHZ(20)) { in uart_set_npcx_baud_rate()
134 } else if (src_clk == MHZ(25)) { in uart_set_npcx_baud_rate()
137 } else if (src_clk == MHZ(30)) { in uart_set_npcx_baud_rate()
140 } else if (src_clk == MHZ(48)) { in uart_set_npcx_baud_rate()
143 } else if (src_clk == MHZ(50)) { in uart_set_npcx_baud_rate()
150 if (src_clk == MHZ(48)) { in uart_set_npcx_baud_rate()
Duart_esp32.c171 uart_sclk_t src_clk; in uart_esp32_config_get() local
174 uart_hal_get_sclk(&data->hal, &src_clk); in uart_esp32_config_get()
175 esp_clk_tree_src_get_freq_hz((soc_module_clk_t)src_clk, in uart_esp32_config_get()
251 uart_sclk_t src_clk; in uart_esp32_configure() local
332 uart_hal_get_sclk(&data->hal, &src_clk); in uart_esp32_configure()
333 esp_clk_tree_src_get_freq_hz((soc_module_clk_t)src_clk, in uart_esp32_configure()