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Searched refs:pulse_cycles (Results 1 – 25 of 48) sorted by relevance

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/Zephyr-latest/drivers/pwm/
Dpwm_nrf_sw.c74 uint32_t pulse_cycles[PWM_0_MAP_SIZE]; member
99 uint32_t pulse_cycles) in pwm_period_check() argument
104 if ((pulse_cycles == 0U) || (pulse_cycles == period_cycles)) { in pwm_period_check()
111 (data->pulse_cycles[i] != 0U) && in pwm_period_check()
121 uint32_t period_cycles, uint32_t pulse_cycles, in pwm_nrf_sw_set_cycles() argument
145 pulse_cycles); in pwm_nrf_sw_set_cycles()
172 channel, period_cycles, pulse_cycles); in pwm_nrf_sw_set_cycles()
186 if (pulse_cycles == 0 || pulse_cycles == period_cycles) { in pwm_nrf_sw_set_cycles()
188 pulse_cycles == 0 ? !active_level in pwm_nrf_sw_set_cycles()
195 data->pulse_cycles[channel] = 0U; in pwm_nrf_sw_set_cycles()
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Dpwm_xlnx_axi_timer.c67 uint32_t pulse_cycles, pwm_flags_t flags) in xlnx_axi_timer_set_cycles() argument
79 LOG_DBG("period = 0x%08x, pulse = 0x%08x", period_cycles, pulse_cycles); in xlnx_axi_timer_set_cycles()
81 if (pulse_cycles == 0) { in xlnx_axi_timer_set_cycles()
89 } else if (pulse_cycles == period_cycles) { in xlnx_axi_timer_set_cycles()
122 if ((period_cycles - pulse_cycles) < 2) { in xlnx_axi_timer_set_cycles()
128 tlr1 = period_cycles - pulse_cycles - 2; in xlnx_axi_timer_set_cycles()
130 if (pulse_cycles < 2) { in xlnx_axi_timer_set_cycles()
136 tlr1 = pulse_cycles - 2; in xlnx_axi_timer_set_cycles()
Dpwm_rcar.c90 uint32_t *period_cycles, uint32_t *pulse_cycles) in pwm_rcar_update_clk() argument
106 *pulse_cycles /= 2; in pwm_rcar_update_clk()
120 *pulse_cycles *= 2; in pwm_rcar_update_clk()
136 uint32_t pulse_cycles, pwm_flags_t flags) in pwm_rcar_set_cycles() argument
151 if (period_cycles == 0U || pulse_cycles == 0U || pulse_cycles > period_cycles) { in pwm_rcar_set_cycles()
157 config->reg_addr, pulse_cycles, period_cycles, in pwm_rcar_set_cycles()
158 (pulse_cycles * 100U / period_cycles)); in pwm_rcar_set_cycles()
176 ret = pwm_rcar_update_clk(config, channel, &period_cycles, &pulse_cycles); in pwm_rcar_set_cycles()
191 reg_val |= (pulse_cycles << RCAR_PWM_CNT_PH_SHIFT); in pwm_rcar_set_cycles()
Dpwm_mcux_ctimer.c128 uint32_t pulse_cycles, uint32_t period_channel, in mcux_ctimer_pwm_update_state() argument
136 data->channel_states[pulse_channel].cycles = pulse_cycles; in mcux_ctimer_pwm_update_state()
145 uint32_t period_cycles, uint32_t pulse_cycles, in mcux_ctimer_pwm_set_cycles() argument
172 if (pulse_cycles == 0) { in mcux_ctimer_pwm_set_cycles()
174 pulse_cycles = period_cycles + 1; in mcux_ctimer_pwm_set_cycles()
176 pulse_cycles = period_cycles - pulse_cycles; in mcux_ctimer_pwm_set_cycles()
181 pulse_cycles, false); in mcux_ctimer_pwm_set_cycles()
186 mcux_ctimer_pwm_update_state(data, pulse_channel, pulse_cycles, period_channel, in mcux_ctimer_pwm_set_cycles()
Dpwm_handlers.c53 uint32_t *pulse_cycles, in z_vrfy_pwm_capture_cycles() argument
71 if (pulse_cycles != NULL) { in z_vrfy_pwm_capture_cycles()
72 K_OOPS(k_usermode_to_copy(pulse_cycles, &pulse, in z_vrfy_pwm_capture_cycles()
73 sizeof(*pulse_cycles))); in z_vrfy_pwm_capture_cycles()
Dpwm_ifx_cat1.c93 uint32_t period_cycles, uint32_t pulse_cycles, pwm_flags_t flags) in ifx_cat1_pwm_set_cycles() argument
99 ((period_cycles > UINT16_MAX) || (pulse_cycles > UINT16_MAX))) { in ifx_cat1_pwm_set_cycles()
104 if (pulse_cycles > UINT16_MAX) { in ifx_cat1_pwm_set_cycles()
105 LOG_ERR("Pulse cycles more than 16-bits (%u)", pulse_cycles); in ifx_cat1_pwm_set_cycles()
110 if ((period_cycles == 0) || (pulse_cycles == 0)) { in ifx_cat1_pwm_set_cycles()
114 Cy_TCPWM_PWM_SetCompare0Val(PWM_REG_BASE, data->pwm_num, pulse_cycles); in ifx_cat1_pwm_set_cycles()
Dpwm_nxp_s32_emios.c106 uint32_t period_cycles, uint32_t pulse_cycles, in pwm_nxp_s32_set_cycles_opwfmb() argument
124 config->base->CH.UC[channel].A = pulse_cycles; in pwm_nxp_s32_set_cycles_opwfmb()
132 if (pulse_cycles) { in pwm_nxp_s32_set_cycles_opwfmb()
141 if (pulse_cycles) { in pwm_nxp_s32_set_cycles_opwfmb()
153 config->base->CH.UC[channel].A = pulse_cycles; in pwm_nxp_s32_set_cycles_opwfmb()
164 uint32_t period_cycles, uint32_t pulse_cycles, in pwm_nxp_s32_set_cycles_opwmcb() argument
177 if (pulse_cycles == 0) { in pwm_nxp_s32_set_cycles_opwmcb()
178 pulse_cycles = EMIOS_PWM_IP_MAX_CNT_VAL; in pwm_nxp_s32_set_cycles_opwmcb()
179 } else if (pulse_cycles == period_cycles) { in pwm_nxp_s32_set_cycles_opwmcb()
180 pulse_cycles = 1; in pwm_nxp_s32_set_cycles_opwmcb()
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Dpwm_gd32.c61 uint32_t period_cycles, uint32_t pulse_cycles, in pwm_gd32_set_cycles() argument
91 TIMER_CH0CV(config->reg) = pulse_cycles; in pwm_gd32_set_cycles()
94 TIMER_CH1CV(config->reg) = pulse_cycles; in pwm_gd32_set_cycles()
97 TIMER_CH2CV(config->reg) = pulse_cycles; in pwm_gd32_set_cycles()
100 TIMER_CH3CV(config->reg) = pulse_cycles; in pwm_gd32_set_cycles()
Dpwm_mcux.c43 uint32_t period_cycles, uint32_t pulse_cycles, in mcux_pwm_set_cycles_internal() argument
103 (uint16_t)pulse_cycles); in mcux_pwm_set_cycles_internal()
116 (uint16_t)pulse_cycles); in mcux_pwm_set_cycles_internal()
130 (uint16_t)pulse_cycles); in mcux_pwm_set_cycles_internal()
137 (uint16_t)pulse_cycles); in mcux_pwm_set_cycles_internal()
146 uint32_t period_cycles, uint32_t pulse_cycles, in mcux_pwm_set_cycles() argument
170 result = mcux_pwm_set_cycles_internal(dev, channel, period_cycles, pulse_cycles, flags); in mcux_pwm_set_cycles()
Dpwm_max32.c36 uint32_t pulse_cycles, pwm_flags_t flags) in api_set_cycles() argument
55 if (pulse_cycles == 0) { in api_set_cycles()
57 pulse_cycles = period_cycles; in api_set_cycles()
81 ret = MXC_TMR_SetPWM(regs, pulse_cycles); in api_set_cycles()
Dpwm_ene_kb1200.c28 uint32_t pulse_cycles, pwm_flags_t flags) in pwm_kb1200_set_cycles() argument
48 if (pulse_cycles == 0) { in pwm_kb1200_set_cycles()
53 high_len = (pulse_cycles / prescaler); in pwm_kb1200_set_cycles()
Dpwm_imx.c50 uint32_t period_cycles, uint32_t pulse_cycles, in imx_pwm_set_cycles() argument
72 " duty_cycle=%d\n", enabled, pulse_cycles, period_cycles, in imx_pwm_set_cycles()
73 (pulse_cycles * 100U / period_cycles)); in imx_pwm_set_cycles()
119 PWM_PWMSAR_REG(config->base) = pulse_cycles; in imx_pwm_set_cycles()
Dpwm_xmc4xxx_ccu4.c52 uint32_t period_cycles, uint32_t pulse_cycles, in pwm_xmc4xxx_ccu4_set_cycles() argument
63 if (period_cycles == 0 || period_cycles > UINT16_MAX + 1 || pulse_cycles > UINT16_MAX) { in pwm_xmc4xxx_ccu4_set_cycles()
69 slice->CRS = period_cycles - pulse_cycles; in pwm_xmc4xxx_ccu4_set_cycles()
Dpwm_sam0_tcc.c58 uint32_t period_cycles, uint32_t pulse_cycles, in pwm_sam0_set_cycles() argument
71 if (period_cycles >= top || pulse_cycles >= top) { in pwm_sam0_set_cycles()
81 regs->CCBUF[channel].reg = TCC_CCBUF_CCBUF(pulse_cycles); in pwm_sam0_set_cycles()
85 regs->CCB[channel].reg = TCC_CCB_CCB(pulse_cycles); in pwm_sam0_set_cycles()
Dpwm_b91.c59 uint32_t period_cycles, uint32_t pulse_cycles, in pwm_b91_set_cycles() argument
71 (pulse_cycles > 0xFFFFu)) { in pwm_b91_set_cycles()
83 pwm_set_tcmp(channel, pulse_cycles); in pwm_b91_set_cycles()
Dpwm_xmc4xxx_ccu8.c88 uint32_t period_cycles, uint32_t pulse_cycles, in pwm_xmc4xxx_ccu8_set_cycles() argument
101 if (period_cycles == 0 || period_cycles > UINT16_MAX + 1 || pulse_cycles > UINT16_MAX) { in pwm_xmc4xxx_ccu8_set_cycles()
109 slice->CR2S = period_cycles - pulse_cycles; in pwm_xmc4xxx_ccu8_set_cycles()
111 slice->CR1S = period_cycles - pulse_cycles; in pwm_xmc4xxx_ccu8_set_cycles()
Dpwm_litex.c37 uint32_t pulse_cycles, pwm_flags_t flags) in pwm_litex_set_cycles() argument
46 litex_write32(pulse_cycles, cfg->reg_width); in pwm_litex_set_cycles()
Dpwm_sam.c54 uint32_t period_cycles, uint32_t pulse_cycles, in sam_pwm_set_cycles() argument
87 pwm->PWM_CH_NUM[channel].PWM_CDTY = pulse_cycles; in sam_pwm_set_cycles()
93 pwm->PWM_CH_NUM[channel].PWM_CDTYUPD = pulse_cycles; in sam_pwm_set_cycles()
Dpwm_nxp_flexio.c95 uint32_t pulse_cycles, pwm_flags_t flags) in pwm_nxp_flexio_set_cycles() argument
116 if (FLEXIO_PWM_TIMER_CMP_MAX_VALUE <= (uint16_t)pulse_cycles) { in pwm_nxp_flexio_set_cycles()
121 if (FLEXIO_PWM_TIMER_CMP_MAX_VALUE <= (uint16_t)(period_cycles - pulse_cycles)) { in pwm_nxp_flexio_set_cycles()
126 if (pulse_cycles > period_cycles) { in pwm_nxp_flexio_set_cycles()
150 timerConfig.timerCompare = ((uint8_t)(pulse_cycles - 1U)) | in pwm_nxp_flexio_set_cycles()
151 ((uint8_t)(data->period_cycles[channel] - pulse_cycles - 1U) in pwm_nxp_flexio_set_cycles()
Dpwm_capture.c24 uint32_t pulse_cycles, int status, in z_pwm_capture_cycles_callback() argument
30 data->pulse = pulse_cycles; in z_pwm_capture_cycles_callback()
Dpwm_mchp_xec_bbled.c213 uint32_t period_cycles, uint32_t pulse_cycles, in pwm_bbled_xec_set_cycles() argument
229 LOG_DBG("period_cycles = %u pulse_cycles = %u", period_cycles, pulse_cycles); in pwm_bbled_xec_set_cycles()
231 if (pulse_cycles == 0u) { in pwm_bbled_xec_set_cycles()
237 } else if (pulse_cycles >= period_cycles) { in pwm_bbled_xec_set_cycles()
252 dc = ((XEC_PWM_BBLED_DC_MAX + 1) * pulse_cycles / period_cycles); in pwm_bbled_xec_set_cycles()
Dpwm_rpi_pico.c103 uint32_t pulse_cycles, pwm_flags_t flags) in pwm_rpi_set_cycles() argument
132 pulse_cycles /= div_int; in pwm_rpi_set_cycles()
136 pulse_cycles > PWM_RPI_PICO_COUNTER_TOP_MAX) { in pwm_rpi_set_cycles()
143 pwm_set_chan_level(slice, pico_channel, pulse_cycles); in pwm_rpi_set_cycles()
Dpwm_led_esp32.c280 uint32_t period_cycles, uint32_t pulse_cycles, in pwm_led_esp32_set_cycles() argument
295 pulse_cycles = period_cycles - pulse_cycles; in pwm_led_esp32_set_cycles()
303 if ((pulse_cycles == period_cycles) || (pulse_cycles == 0)) { in pwm_led_esp32_set_cycles()
305 pwm_led_esp32_stop(data, channel, (pulse_cycles == period_cycles)); in pwm_led_esp32_set_cycles()
318 double duty_cycle = (double)pulse_cycles / (double)period_cycles; in pwm_led_esp32_set_cycles()
Dpwm_ite_it8801.c84 uint32_t pulse_cycles, pwm_flags_t flags) in pwm_it8801_set_cycles() argument
104 if (pulse_cycles == 0) { in pwm_it8801_set_cycles()
107 duty = pulse_cycles * 256 / period_cycles - 1; in pwm_it8801_set_cycles()
/Zephyr-latest/include/zephyr/drivers/
Dpwm.h394 uint32_t pulse_cycles,
403 uint32_t period_cycles, uint32_t pulse_cycles,
541 uint64_t pulse_cycles; in pwm_set() local
555 pulse_cycles = (pulse * cycles_per_sec) / NSEC_PER_SEC; in pwm_set()
556 if (pulse_cycles > UINT32_MAX) { in pwm_set()
561 (uint32_t)pulse_cycles, flags); in pwm_set()
853 uint32_t pulse_cycles; in pwm_capture_usec() local
857 &pulse_cycles, timeout); in pwm_capture_usec()
867 err = pwm_cycles_to_usec(dev, channel, pulse_cycles, pulse); in pwm_capture_usec()
908 uint32_t pulse_cycles; in pwm_capture_nsec() local
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