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Searched refs:port (Results 1 – 25 of 1510) sorted by relevance

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/Zephyr-Core-3.7.0/tests/drivers/gpio/gpio_api_1pin/src/
Dtest_config.c15 static void pin_get_raw_and_verify(const struct device *port, in pin_get_raw_and_verify() argument
21 val_actual = gpio_pin_get_raw(port, pin); in pin_get_raw_and_verify()
28 static void pin_set_raw_and_verify(const struct device *port, in pin_set_raw_and_verify() argument
32 zassert_equal(gpio_pin_set_raw(port, pin, val), 0, in pin_set_raw_and_verify()
50 const struct device *port; in ZTEST() local
53 port = DEVICE_DT_GET(TEST_NODE); in ZTEST()
54 zassert_true(device_is_ready(port), "GPIO dev is not ready"); in ZTEST()
56 TC_PRINT("Running test on port=%s, pin=%d\n", port->name, TEST_PIN); in ZTEST()
58 ret = gpio_pin_configure(port, TEST_PIN, GPIO_OUTPUT); in ZTEST()
61 pin_set_raw_and_verify(port, TEST_PIN, 1, TEST_POINT(1)); in ZTEST()
[all …]
Dtest_pin.c12 static void pin_get_raw_and_verify(const struct device *port, in pin_get_raw_and_verify() argument
18 val_actual = gpio_pin_get_raw(port, pin); in pin_get_raw_and_verify()
25 static void pin_get_and_verify(const struct device *port, unsigned int pin, in pin_get_and_verify() argument
30 val_actual = gpio_pin_get(port, pin); in pin_get_and_verify()
37 static void pin_set_raw_and_verify(const struct device *port, in pin_set_raw_and_verify() argument
41 zassert_equal(gpio_pin_set_raw(port, pin, val), 0, in pin_set_raw_and_verify()
46 static void pin_set_and_verify(const struct device *port, unsigned int pin, in pin_set_and_verify() argument
50 zassert_equal(gpio_pin_set(port, pin, val), 0, in pin_set_and_verify()
62 const struct device *port; in ZTEST() local
66 port = DEVICE_DT_GET(TEST_NODE); in ZTEST()
[all …]
Dtest_port.c14 static void port_get_raw_and_verify(const struct device *port, in port_get_raw_and_verify() argument
20 zassert_equal(gpio_port_get_raw(port, &val_actual), 0, in port_get_raw_and_verify()
26 static void port_get_and_verify(const struct device *port, in port_get_and_verify() argument
32 zassert_equal(gpio_port_get(port, &val_actual), 0, in port_get_and_verify()
38 static void port_set_masked_raw_and_verify(const struct device *port, in port_set_masked_raw_and_verify() argument
42 zassert_equal(gpio_port_set_masked_raw(port, mask, value), 0, in port_set_masked_raw_and_verify()
47 static void port_set_masked_and_verify(const struct device *port, in port_set_masked_and_verify() argument
51 zassert_equal(gpio_port_set_masked(port, mask, value), 0, in port_set_masked_and_verify()
56 static void port_set_bits_raw_and_verify(const struct device *port, in port_set_bits_raw_and_verify() argument
59 zassert_equal(gpio_port_set_bits_raw(port, pins), 0, in port_set_bits_raw_and_verify()
[all …]
Dtest_pin_interrupt.c16 static void callback_edge(const struct device *port, struct gpio_callback *cb, in callback_edge() argument
24 static void callback_level(const struct device *port, in callback_level() argument
35 ret = gpio_pin_interrupt_configure(port, TEST_PIN, GPIO_INT_DISABLE); in callback_level()
41 static void pin_set_and_verify(const struct device *port, unsigned int pin, in pin_set_and_verify() argument
45 zassert_equal(gpio_pin_set(port, pin, val), 0, in pin_set_and_verify()
53 const struct device *port; in test_gpio_pin_interrupt_edge() local
58 port = DEVICE_DT_GET(TEST_NODE); in test_gpio_pin_interrupt_edge()
59 zassert_true(device_is_ready(port), "GPIO dev is not ready"); in test_gpio_pin_interrupt_edge()
61 TC_PRINT("Running test on port=%s, pin=%d\n", port->name, TEST_PIN); in test_gpio_pin_interrupt_edge()
63 ret = gpio_pin_configure(port, TEST_PIN, GPIO_INPUT | GPIO_OUTPUT); in test_gpio_pin_interrupt_edge()
[all …]
/Zephyr-Core-3.7.0/drivers/xen/
Devents.c29 unsigned int port = (((evtchn_handle_t *)data) - event_channels); in empty_callback() local
31 events_missed[port] = true; in empty_callback()
44 rc = alloc.port; in alloc_unbound_event_channel()
61 rc = alloc.port; in alloc_unbound_event_channel_dom0()
95 int evtchn_close(evtchn_port_t port) in evtchn_close() argument
98 .port = port, in evtchn_close()
104 int evtchn_set_priority(evtchn_port_t port, uint32_t priority) in evtchn_set_priority() argument
107 .port = port, in evtchn_set_priority()
114 void notify_evtchn(evtchn_port_t port) in notify_evtchn() argument
118 __ASSERT(port < EVTCHN_2L_NR_CHANNELS, in notify_evtchn()
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/Zephyr-Core-3.7.0/include/zephyr/arch/arc/v2/
Dsys_io.h26 void sys_out8(uint8_t data, io_port_t port) in sys_out8() argument
28 z_arc_v2_aux_reg_write(port, data); in sys_out8()
32 uint8_t sys_in8(io_port_t port) in sys_in8() argument
34 return (uint8_t)(z_arc_v2_aux_reg_read(port) & 0x000000ff); in sys_in8()
38 void sys_out16(uint16_t data, io_port_t port) in sys_out16() argument
40 z_arc_v2_aux_reg_write(port, data); in sys_out16()
44 uint16_t sys_in16(io_port_t port) in sys_in16() argument
46 return (uint16_t)(z_arc_v2_aux_reg_read(port) & 0x0000ffff); in sys_in16()
50 void sys_out32(uint32_t data, io_port_t port) in sys_out32() argument
52 z_arc_v2_aux_reg_write(port, data); in sys_out32()
[all …]
/Zephyr-Core-3.7.0/drivers/ethernet/
Deth_xlnx_gem_priv.h407 #define ETH_XLNX_GEM_NET_DEV_INIT(port) \ argument
408 ETH_NET_DEVICE_DT_INST_DEFINE(port,\
411 &eth_xlnx_gem##port##_dev_data,\
412 &eth_xlnx_gem##port##_dev_cfg,\
418 #define ETH_XLNX_GEM_DEV_CONFIG(port) \ argument
419 static const struct eth_xlnx_gem_dev_cfg eth_xlnx_gem##port##_dev_cfg = {\
420 .base_addr = DT_REG_ADDR_BY_IDX(DT_INST(port, xlnx_gem), 0),\
421 .config_func = eth_xlnx_gem##port##_irq_config,\
422 .pll_clock_frequency = DT_INST_PROP(port, clock_frequency),\
423 .clk_ctrl_reg_address = DT_REG_ADDR_BY_IDX(DT_INST(port, xlnx_gem), 1),\
[all …]
/Zephyr-Core-3.7.0/subsys/net/lib/ptp/
Dport.c82 static int port_msg_send(struct ptp_port *port, struct ptp_msg *msg, enum ptp_socket idx) in port_msg_send() argument
86 return ptp_transport_send(port, msg, idx); in port_msg_send()
117 static void port_synchronize(struct ptp_port *port, in port_synchronize() argument
131 port_timer_set_timeout(&port->timers.sync, in port_synchronize()
132 port->port_ds.announce_receipt_timeout, in port_synchronize()
133 port->port_ds.log_sync_interval); in port_synchronize()
136 static void port_ds_init(struct ptp_port *port) in port_ds_init() argument
138 struct ptp_port_ds *ds = &port->port_ds; in port_ds_init()
157 struct ptp_port *port = ptp_clock_port_from_iface(pkt->iface); in port_delay_req_timestamp_cb() local
161 if (!port || !msg) { in port_delay_req_timestamp_cb()
[all …]
/Zephyr-Core-3.7.0/drivers/gpio/
Dgpio_handlers.c10 static inline int z_vrfy_gpio_pin_configure(const struct device *port, in z_vrfy_gpio_pin_configure() argument
14 K_OOPS(K_SYSCALL_DRIVER_GPIO(port, pin_configure)); in z_vrfy_gpio_pin_configure()
15 return z_impl_gpio_pin_configure((const struct device *)port, in z_vrfy_gpio_pin_configure()
22 static inline int z_vrfy_gpio_pin_get_config(const struct device *port, in z_vrfy_gpio_pin_get_config() argument
26 K_OOPS(K_SYSCALL_DRIVER_GPIO(port, pin_get_config)); in z_vrfy_gpio_pin_get_config()
29 return z_impl_gpio_pin_get_config(port, pin, flags); in z_vrfy_gpio_pin_get_config()
34 static inline int z_vrfy_gpio_port_get_raw(const struct device *port, in z_vrfy_gpio_port_get_raw() argument
37 K_OOPS(K_SYSCALL_DRIVER_GPIO(port, port_get_raw)); in z_vrfy_gpio_port_get_raw()
39 return z_impl_gpio_port_get_raw((const struct device *)port, in z_vrfy_gpio_port_get_raw()
44 static inline int z_vrfy_gpio_port_set_masked_raw(const struct device *port, in z_vrfy_gpio_port_set_masked_raw() argument
[all …]
Dgpio_andes_atcgpio100.c97 static int gpio_atcgpio100_config(const struct device *port, in gpio_atcgpio100_config() argument
101 struct gpio_atcgpio100_data * const data = port->data; in gpio_atcgpio100_config()
119 sys_write32(pin_mask, GPIO_DSET(port)); in gpio_atcgpio100_config()
121 sys_write32(pin_mask, GPIO_DCLR(port)); in gpio_atcgpio100_config()
127 port_value = sys_read32(GPIO_DIR(port)); in gpio_atcgpio100_config()
128 sys_write32((port_value | pin_mask), GPIO_DIR(port)); in gpio_atcgpio100_config()
145 sys_write32(DF_DEBOUNCED_SETTING, GPIO_DEBC(port)); in gpio_atcgpio100_config()
146 port_value = sys_read32(GPIO_DEBE(port)); in gpio_atcgpio100_config()
147 sys_write32((port_value | pin_mask), GPIO_DEBE(port)); in gpio_atcgpio100_config()
151 port_value = sys_read32(GPIO_DIR(port)); in gpio_atcgpio100_config()
[all …]
Dgpio_emul.c115 get_pins_with_flags(const struct device *port, gpio_port_pins_t mask, in get_pins_with_flags() argument
121 (struct gpio_emul_data *)port->data; in get_pins_with_flags()
123 (const struct gpio_emul_config *)port->config; in get_pins_with_flags()
143 static inline gpio_port_pins_t get_input_pins(const struct device *port) in get_input_pins() argument
145 return get_pins_with_flags(port, GPIO_INPUT, GPIO_INPUT); in get_input_pins()
157 static inline gpio_port_pins_t get_output_pins(const struct device *port) in get_output_pins() argument
159 return get_pins_with_flags(port, GPIO_OUTPUT, GPIO_OUTPUT); in get_output_pins()
170 static inline bool gpio_emul_config_has_caps(const struct device *port, in gpio_emul_config_has_caps() argument
174 (const struct gpio_emul_config *)port->config; in gpio_emul_config_has_caps()
182 static void gpio_emul_gen_interrupt_bits(const struct device *port, in gpio_emul_gen_interrupt_bits() argument
[all …]
Dgpio_psoc6.c45 GPIO_PRT_Type * const port = cfg->regs; in gpio_psoc6_config() local
80 Cy_GPIO_Pin_FastInit(port, pin, drv_mode, pin_val, HSIOM_SEL_GPIO); in gpio_psoc6_config()
81 Cy_GPIO_SetVtrip(port, pin, CY_GPIO_VTRIP_CMOS); in gpio_psoc6_config()
82 Cy_GPIO_SetSlewRate(port, pin, CY_GPIO_SLEW_FAST); in gpio_psoc6_config()
83 Cy_GPIO_SetDriveSel(port, pin, CY_GPIO_DRIVE_FULL); in gpio_psoc6_config()
86 (unsigned int) port, pin, drv_mode, pin_val); in gpio_psoc6_config()
95 GPIO_PRT_Type * const port = cfg->regs; in gpio_psoc6_port_get_raw() local
97 *value = GPIO_PRT_IN(port); in gpio_psoc6_port_get_raw()
99 LOG_DBG("P: 0x%08x, V: 0x%08x", (unsigned int) port, *value); in gpio_psoc6_port_get_raw()
109 GPIO_PRT_Type * const port = cfg->regs; in gpio_psoc6_port_set_masked_raw() local
[all …]
/Zephyr-Core-3.7.0/drivers/misc/timeaware_gpio/
Dtimeaware_gpio_handlers.c9 static inline int z_vrfy_tgpio_port_get_time(const struct device *port, uint64_t *current_time) in z_vrfy_tgpio_port_get_time() argument
11 K_OOPS(Z_SYSCALL_DRIVER_TGPIO(port, get_time)); in z_vrfy_tgpio_port_get_time()
13 return z_impl_tgpio_port_get_time((const struct device *)port, (uint64_t *)current_time); in z_vrfy_tgpio_port_get_time()
17 static inline int z_vrfy_tgpio_port_get_cycles_per_second(const struct device *port, in z_vrfy_tgpio_port_get_cycles_per_second() argument
20 K_OOPS(Z_SYSCALL_DRIVER_TGPIO(port, cyc_per_sec)); in z_vrfy_tgpio_port_get_cycles_per_second()
22 return z_impl_tgpio_port_get_cycles_per_second((const struct device *)port, in z_vrfy_tgpio_port_get_cycles_per_second()
27 static inline int z_vrfy_tgpio_pin_periodic_output(const struct device *port, uint32_t pin, in z_vrfy_tgpio_pin_periodic_output() argument
31 K_OOPS(Z_SYSCALL_DRIVER_TGPIO(port, set_perout)); in z_vrfy_tgpio_pin_periodic_output()
32 return z_impl_tgpio_pin_periodic_output((const struct device *)port, pin, start_time, in z_vrfy_tgpio_pin_periodic_output()
37 static inline int z_vrfy_tgpio_pin_disable(const struct device *port, uint32_t pin) in z_vrfy_tgpio_pin_disable() argument
[all …]
/Zephyr-Core-3.7.0/include/zephyr/drivers/
Dgpio.h290 const struct device *port; member
333 .port = DEVICE_DT_GET(DT_GPIO_CTLR_BY_IDX(node_id, prop, idx)),\
726 typedef void (*gpio_callback_handler_t)(const struct device *port,
793 int (*pin_configure)(const struct device *port, gpio_pin_t pin,
796 int (*pin_get_config)(const struct device *port, gpio_pin_t pin,
799 int (*port_get_raw)(const struct device *port,
801 int (*port_set_masked_raw)(const struct device *port,
804 int (*port_set_bits_raw)(const struct device *port,
806 int (*port_clear_bits_raw)(const struct device *port,
808 int (*port_toggle_bits)(const struct device *port,
[all …]
/Zephyr-Core-3.7.0/subsys/net/l2/ethernet/gptp/
Dgptp_private.h28 #define GPTP_STATS_INC(port, var) (GPTP_PORT_PARAM_DS(port)->var++) argument
30 #define GPTP_STATS_INC(port, var)
42 bool gptp_is_slave_port(int port);
83 void gptp_update_pdelay_req_interval(int port, int8_t log_val);
92 void gptp_update_sync_interval(int port, int8_t log_val);
102 void gptp_update_announce_interval(int port, int8_t log_val);
127 void gptp_change_port_state(int port, enum gptp_port_state state);
129 #define gptp_change_port_state(port, state) \ argument
130 gptp_change_port_state_debug(port, state, __func__, __LINE__)
132 void gptp_change_port_state_debug(int port, enum gptp_port_state state,
[all …]
Dgptp_mi.c72 void gptp_change_port_state_debug(int port, enum gptp_port_state state, in gptp_change_port_state_debug() argument
76 void gptp_change_port_state(int port, enum gptp_port_state state) in gptp_change_port_state_debug()
81 if (global_ds->selected_role[port] == state) { in gptp_change_port_state_debug()
86 NET_DBG("[%d] state %s -> %s (%s():%d)", port, in gptp_change_port_state_debug()
87 state2str(global_ds->selected_role[port]), in gptp_change_port_state_debug()
91 global_ds->selected_role[port] = state; in gptp_change_port_state_debug()
96 int port, in gptp_change_pa_info_state_debug() argument
103 int port, in gptp_change_pa_info_state_debug()
113 NET_DBG("[%d] PA info state %s -> %s (%s():%d)", port, in gptp_change_pa_info_state_debug()
124 int port; in gptp_mi_half_sync_itv_timeout() local
[all …]
Dgptp.c41 int port = net_eth_get_ptp_port(iface) + 1; in gptp_get_port_number() local
43 if (port >= GPTP_PORT_START && port < GPTP_PORT_END) { in gptp_get_port_number()
44 return port; in gptp_get_port_number()
47 for (port = GPTP_PORT_START; port < GPTP_PORT_END; port++) { in gptp_get_port_number()
48 if (GPTP_PORT_IFACE(port) == iface) { in gptp_get_port_number()
49 return port; in gptp_get_port_number()
56 bool gptp_is_slave_port(int port) in gptp_is_slave_port() argument
58 return (GPTP_GLOBAL_DS()->selected_role[port] == GPTP_PORT_SLAVE); in gptp_is_slave_port()
66 static void gptp_compute_clock_identity(int port) in gptp_compute_clock_identity() argument
68 struct net_if *iface = GPTP_PORT_IFACE(port); in gptp_compute_clock_identity()
[all …]
Dgptp_md.c117 static int gptp_set_md_sync_receive(int port, in gptp_set_md_sync_receive() argument
128 state = &GPTP_PORT_STATE(port)->sync_rcv; in gptp_set_md_sync_receive()
133 port_ds = GPTP_PORT_DS(port); in gptp_set_md_sync_receive()
181 static void gptp_md_pdelay_reset(int port) in gptp_md_pdelay_reset() argument
188 state = &GPTP_PORT_STATE(port)->pdelay_req; in gptp_md_pdelay_reset()
189 port_ds = GPTP_PORT_DS(port); in gptp_md_pdelay_reset()
200 static void gptp_md_pdelay_check_multiple_resp(int port) in gptp_md_pdelay_check_multiple_resp() argument
206 state = &GPTP_PORT_STATE(port)->pdelay_req; in gptp_md_pdelay_check_multiple_resp()
207 port_ds = GPTP_PORT_DS(port); in gptp_md_pdelay_check_multiple_resp()
236 static void gptp_md_compute_pdelay_rate_ratio(int port) in gptp_md_compute_pdelay_rate_ratio() argument
[all …]
/Zephyr-Core-3.7.0/include/zephyr/arch/x86/ia32/
Dsys_io.h19 void sys_io_set_bit(io_port_t port, unsigned int bit) in sys_io_set_bit() argument
27 : "a" (reg), "Nd" (port), "Ir" (bit)); in sys_io_set_bit()
31 void sys_io_clear_bit(io_port_t port, unsigned int bit) in sys_io_clear_bit() argument
39 : "a" (reg), "Nd" (port), "Ir" (bit)); in sys_io_clear_bit()
43 int sys_io_test_bit(io_port_t port, unsigned int bit) in sys_io_test_bit() argument
50 : "Nd" (port), "Ir" (bit)); in sys_io_test_bit()
56 int sys_io_test_and_set_bit(io_port_t port, unsigned int bit) in sys_io_test_and_set_bit() argument
60 ret = sys_io_test_bit(port, bit); in sys_io_test_and_set_bit()
61 sys_io_set_bit(port, bit); in sys_io_test_and_set_bit()
67 int sys_io_test_and_clear_bit(io_port_t port, unsigned int bit) in sys_io_test_and_clear_bit() argument
[all …]
/Zephyr-Core-3.7.0/dts/arm/renesas/ra/
Dra-cm4-common.dtsi131 interrupt-names = "port-irq2", "port-irq3", "port-irq6",
132 "port-irq7", "port-irq10", "port-irq15";
133 port-irq2-pins = <2>;
134 port-irq3-pins = <4>;
135 port-irq6-pins = <0>;
136 port-irq7-pins = <1 15>;
137 port-irq10-pins = <5>;
138 port-irq15-pins = <11>;
152 interrupt-names = "port-irq0", "port-irq1", "port-irq2",
153 "port-irq3", "port-irq4";
[all …]
/Zephyr-Core-3.7.0/drivers/pinctrl/
Dpinctrl_numicro.c26 #define REG_MFP(port, pin) (*(volatile uint32_t *)((uint32_t)DT_INST_REG_ADDR_BY_NAME(0, mfp) + \ argument
27 ((port) * 8) + \
30 #define REG_MFOS(port) (*(volatile uint32_t *)((uint32_t)DT_INST_REG_ADDR_BY_NAME(0, mfos) + \ argument
31 ((port) * 4)))
55 GPIO_T *port; in gpio_configure() local
65 port = (GPIO_T *)gpio_port_addrs[port_idx]; in gpio_configure()
73 port->MODE = (port->MODE & ~MODE_MASK(pin_idx)) | in gpio_configure()
75 port->DBEN = (port->DBEN & ~BIT(pin_idx)) | in gpio_configure()
77 port->SMTEN = (port->SMTEN & ~BIT(pin_idx)) | in gpio_configure()
79 port->DINOFF = (port->SMTEN & ~DINOFF_MASK(pin_idx)) | in gpio_configure()
[all …]
/Zephyr-Core-3.7.0/include/zephyr/dt-bindings/pinctrl/renesas/
Dpinctrl-ra-common.h25 #define RA_PINCFG(port, pin, psel, opt) \ argument
27 (((port)&PORT_MASK) << PORT_POS) | ((((port) >> 3) & PORT4_MASK) << PORT4_POS) | \
31 #define RA_PINCFG__40(port, pin, psel, opt) RA_PINCFG(port, pin, psel, opt) argument
35 #define RA_PINCFG__48(port, pin, psel, opt) RA_PINCFG(port, pin, psel, opt) argument
39 #define RA_PINCFG__64(port, pin, psel, opt) RA_PINCFG(port, pin, psel, opt) argument
43 #define RA_PINCFG_100(port, pin, psel, opt) RA_PINCFG(port, pin, psel, opt) argument
/Zephyr-Core-3.7.0/drivers/pinctrl/renesas/rz/
Dpinctrl_rzt2m.c17 #define PMC(port) (PORT_NSR + 0x400 + port) argument
19 #define PFC(port) (PORT_NSR + 0x600 + (0x4 * port)) argument
21 #define DRCTL(port, pin) (PORT_NSR + 0xa00 + (0x8 * port) + pin) argument
23 #define RSELP(port) (PTADR + port) argument
36 uint8_t rselp = sys_read8(RSELP(pin->port)); in pinctrl_configure_pin()
37 uint32_t pfc = sys_read32(PFC(pin->port)) & ~(PFC_FUNC_MASK(pin->pin)); in pinctrl_configure_pin()
38 uint8_t pmc = sys_read8(PMC(pin->port)); in pinctrl_configure_pin()
41 sys_write8(rselp | BIT(pin->pin), RSELP(pin->port)); in pinctrl_configure_pin()
45 DRCTL(pin->port, pin->pin)); in pinctrl_configure_pin()
48 sys_write32(pfc | pin->func << (pin->pin * 4), PFC(pin->port)); in pinctrl_configure_pin()
[all …]
/Zephyr-Core-3.7.0/samples/basic/button/src/
Dmain.c47 button.port->name); in main()
54 ret, button.port->name, button.pin); in main()
62 ret, button.port->name, button.pin); in main()
67 gpio_add_callback(button.port, &button_cb_data); in main()
68 printk("Set up button at %s pin %d\n", button.port->name, button.pin); in main()
70 if (led.port && !gpio_is_ready_dt(&led)) { in main()
72 ret, led.port->name); in main()
73 led.port = NULL; in main()
75 if (led.port) { in main()
79 ret, led.port->name, led.pin); in main()
[all …]
/Zephyr-Core-3.7.0/drivers/pinctrl/renesas/ra/
Dpinctrl_renesas_ra.c21 static inline uint32_t pinctrl_ra_read_PmnFPS(size_t port, size_t pin) in pinctrl_ra_read_PmnFPS() argument
23 return sys_read32(DT_INST_REG_ADDR_BY_NAME(0, pfs) + (port * PIN_NUM + pin) * 4); in pinctrl_ra_read_PmnFPS()
26 static inline void pinctrl_ra_write_PmnFPS(size_t port, size_t pin, uint32_t value) in pinctrl_ra_write_PmnFPS() argument
28 sys_write32(value, DT_INST_REG_ADDR_BY_NAME(0, pfs) + (port * PIN_NUM + pin) * 4); in pinctrl_ra_write_PmnFPS()
31 static inline uint8_t pinctrl_ra_read_PMISC_PWPR(size_t port, size_t pin) in pinctrl_ra_read_PMISC_PWPR() argument
47 pincfg.port = 0; in pinctrl_ra_configure_pfs()
51 uint32_t val = pinctrl_ra_read_PmnFPS(pinc->port, pinc->pin); in pinctrl_ra_configure_pfs()
53 pinctrl_ra_write_PmnFPS(pinc->port, pinc->pin, val & ~(BIT(PmnPFS_PMR_POS))); in pinctrl_ra_configure_pfs()
54 pinctrl_ra_write_PmnFPS(pinc->port, pinc->pin, pincfg.config & ~PmnPFS_PMR_POS); in pinctrl_ra_configure_pfs()
57 pinctrl_ra_write_PmnFPS(pinc->port, pinc->pin, pincfg.config); in pinctrl_ra_configure_pfs()
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