Home
last modified time | relevance | path

Searched refs:bit (Results 1 – 25 of 680) sorted by relevance

12345678910>>...28

/Zephyr-Core-3.7.0/tests/kernel/common/src/
Dbitfield.c14 #define BIT_INDEX(bit) ((3 - ((bit >> 3) & 0x3)) + 4*(bit >> 5)) argument
16 #define BIT_INDEX(bit) (bit >> 3) argument
18 #define BIT_VAL(bit) (1 << (bit & 0x7)) argument
41 unsigned int bit; in ZTEST()
46 for (bit = 0U; bit < 32; ++bit) { in ZTEST()
47 sys_set_bit((mem_addr_t)&b1, bit); in ZTEST()
49 zassert_equal(b1, (1 << bit), in ZTEST()
50 "sys_set_bit failed on bit %d\n", bit); in ZTEST()
52 zassert_true(sys_test_bit((mem_addr_t)&b1, bit), in ZTEST()
53 "sys_test_bit did not detect bit %d\n", bit); in ZTEST()
[all …]
Dbitarray.c17 #define BIT_INDEX(bit) ((3 - ((bit >> 3) & 0x3)) + 4*(bit >> 5)) argument
19 #define BIT_INDEX(bit) (bit >> 3) argument
21 #define BIT_VAL(bit) (1 << (bit & 0x7)) argument
132 size_t bit, bundle_idx, bit_idx_in_bundle; in ZTEST() local
141 for (bit = 0U; bit < ba.num_bits; ++bit) { in ZTEST()
142 bundle_idx = bit / (sizeof(ba.bundles[0]) * 8); in ZTEST()
143 bit_idx_in_bundle = bit % (sizeof(ba.bundles[0]) * 8); in ZTEST()
145 ret = sys_bitarray_set_bit(&ba, bit); in ZTEST()
147 "sys_bitarray_set_bit failed on bit %d", bit); in ZTEST()
149 "sys_bitarray_set_bit did not set bit %d\n", bit); in ZTEST()
[all …]
/Zephyr-Core-3.7.0/include/zephyr/arch/common/
Dsys_bitops.h24 static ALWAYS_INLINE void sys_set_bit(mem_addr_t addr, unsigned int bit) in sys_set_bit() argument
28 *(volatile uint32_t *)addr = temp | (1 << bit); in sys_set_bit()
31 static ALWAYS_INLINE void sys_clear_bit(mem_addr_t addr, unsigned int bit) in sys_clear_bit() argument
35 *(volatile uint32_t *)addr = temp & ~(1 << bit); in sys_clear_bit()
38 static ALWAYS_INLINE int sys_test_bit(mem_addr_t addr, unsigned int bit) in sys_test_bit() argument
42 return temp & (1 << bit); in sys_test_bit()
60 void sys_bitfield_set_bit(mem_addr_t addr, unsigned int bit) in sys_bitfield_set_bit() argument
65 sys_set_bit(addr + ((bit >> 5) << 2), bit & 0x1F); in sys_bitfield_set_bit()
69 void sys_bitfield_clear_bit(mem_addr_t addr, unsigned int bit) in sys_bitfield_clear_bit() argument
71 sys_clear_bit(addr + ((bit >> 5) << 2), bit & 0x1F); in sys_bitfield_clear_bit()
[all …]
Dffs.h63 int bit; in find_lsb_set()
69 for (bit = 0; bit < 32; bit++) { in find_lsb_set()
70 if ((op & (1 << bit)) != 0) { in find_lsb_set()
71 return (bit + 1); in find_lsb_set()
/Zephyr-Core-3.7.0/lib/posix/options/
Dspinlock.c48 size_t bit; in get_posix_spinlock() local
56 bit = to_posix_spinlock_idx(*lock); in get_posix_spinlock()
62 if (sys_bitarray_test_bit(&posix_spinlock_bitarray, bit, &actually_initialized) < 0) { in get_posix_spinlock()
71 return (struct k_spinlock *)&posix_spinlock_pool[bit]; in get_posix_spinlock()
77 size_t bit; in pthread_spin_init() local
85 ret = sys_bitarray_alloc(&posix_spinlock_bitarray, 1, &bit); in pthread_spin_init()
90 *lock = mark_pthread_obj_initialized(bit); in pthread_spin_init()
98 size_t bit; in pthread_spin_destroy() local
107 bit = posix_spinlock_to_offset(l); in pthread_spin_destroy()
108 err = sys_bitarray_free(&posix_spinlock_bitarray, 1, bit); in pthread_spin_destroy()
[all …]
Dmutex.c56 size_t bit = to_posix_mutex_idx(mu); in get_posix_mutex() local
65 if (sys_bitarray_test_bit(&posix_mutex_bitarray, bit, &actually_initialized) < 0) { in get_posix_mutex()
76 return &posix_mutex_pool[bit]; in get_posix_mutex()
82 size_t bit; in to_posix_mutex() local
90 if (sys_bitarray_alloc(&posix_mutex_bitarray, 1, &bit) < 0) { in to_posix_mutex()
96 *mu = mark_pthread_obj_initialized(bit); in to_posix_mutex()
99 m = &posix_mutex_pool[bit]; in to_posix_mutex()
110 size_t bit; in acquire_mutex() local
125 bit = posix_mutex_to_offset(m); in acquire_mutex()
126 type = posix_mutex_type[bit]; in acquire_mutex()
[all …]
Dbarrier.c46 size_t bit = to_posix_barrier_idx(b); in get_posix_barrier() local
54 if (sys_bitarray_test_bit(&posix_barrier_bitarray, bit, &actually_initialized) < 0) { in get_posix_barrier()
63 return &posix_barrier_pool[bit]; in get_posix_barrier()
110 size_t bit; in pthread_barrier_init() local
117 if (sys_bitarray_alloc(&posix_barrier_bitarray, 1, &bit) < 0) { in pthread_barrier_init()
121 bar = &posix_barrier_pool[bit]; in pthread_barrier_init()
125 *b = mark_pthread_obj_initialized(bit); in pthread_barrier_init()
133 size_t bit; in pthread_barrier_destroy() local
151 bit = posix_barrier_to_offset(bar); in pthread_barrier_destroy()
152 err = sys_bitarray_free(&posix_barrier_bitarray, 1, bit); in pthread_barrier_destroy()
/Zephyr-Core-3.7.0/include/zephyr/arch/x86/ia32/
Dsys_io.h19 void sys_io_set_bit(io_port_t port, unsigned int bit) in sys_io_set_bit() argument
27 : "a" (reg), "Nd" (port), "Ir" (bit)); in sys_io_set_bit()
31 void sys_io_clear_bit(io_port_t port, unsigned int bit) in sys_io_clear_bit() argument
39 : "a" (reg), "Nd" (port), "Ir" (bit)); in sys_io_clear_bit()
43 int sys_io_test_bit(io_port_t port, unsigned int bit) in sys_io_test_bit() argument
50 : "Nd" (port), "Ir" (bit)); in sys_io_test_bit()
56 int sys_io_test_and_set_bit(io_port_t port, unsigned int bit) in sys_io_test_and_set_bit() argument
60 ret = sys_io_test_bit(port, bit); in sys_io_test_and_set_bit()
61 sys_io_set_bit(port, bit); in sys_io_test_and_set_bit()
67 int sys_io_test_and_clear_bit(io_port_t port, unsigned int bit) in sys_io_test_and_clear_bit() argument
[all …]
/Zephyr-Core-3.7.0/include/zephyr/sys/
Datomic.h77 #define ATOMIC_MASK(bit) BIT((unsigned long)(bit) & (ATOMIC_BITS - 1U)) argument
78 #define ATOMIC_ELEM(addr, bit) ((addr) + ((bit) / ATOMIC_BITS)) argument
127 static inline bool atomic_test_bit(const atomic_t *target, int bit) in atomic_test_bit() argument
129 atomic_val_t val = atomic_get(ATOMIC_ELEM(target, bit)); in atomic_test_bit()
131 return (1 & (val >> (bit & (ATOMIC_BITS - 1)))) != 0; in atomic_test_bit()
147 static inline bool atomic_test_and_clear_bit(atomic_t *target, int bit) in atomic_test_and_clear_bit() argument
149 atomic_val_t mask = ATOMIC_MASK(bit); in atomic_test_and_clear_bit()
152 old = atomic_and(ATOMIC_ELEM(target, bit), ~mask); in atomic_test_and_clear_bit()
170 static inline bool atomic_test_and_set_bit(atomic_t *target, int bit) in atomic_test_and_set_bit() argument
172 atomic_val_t mask = ATOMIC_MASK(bit); in atomic_test_and_set_bit()
[all …]
/Zephyr-Core-3.7.0/drivers/clock_control/
Dbeetle_clock_control.c33 uint8_t bit, enum arm_soc_state_t state) in beetle_set_clock() argument
41 base[0] |= (1 << bit); in beetle_set_clock()
44 base[2] |= (1 << bit); in beetle_set_clock()
47 base[4] |= (1 << bit); in beetle_set_clock()
56 static inline void beetle_ahb_set_clock_on(uint8_t bit, in beetle_ahb_set_clock_on() argument
60 bit, state); in beetle_ahb_set_clock_on()
63 static inline void beetle_ahb_set_clock_off(uint8_t bit, in beetle_ahb_set_clock_off() argument
67 bit, state); in beetle_ahb_set_clock_off()
70 static inline void beetle_apb_set_clock_on(uint8_t bit, in beetle_apb_set_clock_on() argument
74 bit, state); in beetle_apb_set_clock_on()
[all …]
/Zephyr-Core-3.7.0/include/zephyr/arch/arc/v2/
Dsys_io.h62 void sys_io_set_bit(io_port_t port, unsigned int bit) in sys_io_set_bit() argument
71 "r" (reg), "ir" (bit) in sys_io_set_bit()
76 void sys_io_clear_bit(io_port_t port, unsigned int bit) in sys_io_clear_bit() argument
85 "r" (reg), "ir" (bit) in sys_io_clear_bit()
90 int sys_io_test_bit(io_port_t port, unsigned int bit) in sys_io_test_bit() argument
101 "r" (reg), "ir" (bit), "i" (status) in sys_io_test_bit()
108 int sys_io_test_and_set_bit(io_port_t port, unsigned int bit) in sys_io_test_and_set_bit() argument
112 ret = sys_io_test_bit(port, bit); in sys_io_test_and_set_bit()
113 sys_io_set_bit(port, bit); in sys_io_test_and_set_bit()
119 int sys_io_test_and_clear_bit(io_port_t port, unsigned int bit) in sys_io_test_and_clear_bit() argument
[all …]
/Zephyr-Core-3.7.0/soc/atmel/sam0/common/
Dsoc_samd2x.c54 while (!SYSCTRL->PCLKSR.bit.OSC8MRDY) { in osc8m_init()
63 while (GCLK->STATUS.bit.SYNCBUSY) { in osc8m_init()
71 while (GCLK->STATUS.bit.SYNCBUSY) { in osc8m_init()
92 while (!SYSCTRL->PCLKSR.bit.OSC32KRDY) { in osc32k_init()
121 while (!SYSCTRL->PCLKSR.bit.XOSCRDY) { in xosc_init()
140 while (!SYSCTRL->PCLKSR.bit.XOSC32KRDY) { in xosc32k_init()
166 while (GCLK->STATUS.bit.SYNCBUSY) { in dfll48m_init()
172 while (GCLK->STATUS.bit.SYNCBUSY) { in dfll48m_init()
201 while (!SYSCTRL->PCLKSR.bit.DFLLRDY) { in dfll48m_init()
203 SYSCTRL->DFLLCTRL.bit.ENABLE = 1; in dfll48m_init()
[all …]
Dsoc_saml2x.c38 GCLK->GENCTRL[0].bit.SRC = GCLK_GENCTRL_SRC_OSCULP32K_Val; in gclk_reset()
39 OSCCTRL->OSC16MCTRL.bit.ENABLE = 0; in gclk_reset()
63 while (!OSC32KCTRL->STATUS.bit.OSC32KRDY) { in osc32k_init()
84 while (!OSC32KCTRL->STATUS.bit.XOSC32KRDY) { in xosc32k_init()
101 while (!OSCCTRL->STATUS.bit.OSC16MRDY) { in osc16m_init()
185 while (!OSCCTRL->STATUS.bit.DFLLRDY) { in dfll48m_init()
187 OSCCTRL->DFLLCTRL.bit.ENABLE = 1; in dfll48m_init()
191 while (!OSCCTRL->STATUS.bit.DFLLLCKC || !OSCCTRL->STATUS.bit.DFLLLCKF) { in dfll48m_init()
199 NVMCTRL->CTRLB.bit.RWS = 2; in flash_waitstates_init()
204 PM->PLCFG.bit.PLDIS = 0; in pm_init()
[all …]
Dsoc_samc2x.c21 NVMCTRL->CTRLB.bit.RWS = NVMCTRL_CTRLB_RWS_HALF_Val; in flash_waitstates_init()
27 OSCCTRL->OSC48MDIV.bit.DIV = 0; in osc48m_init()
28 while (OSCCTRL->OSC48MSYNCBUSY.bit.OSC48MDIV) { in osc48m_init()
30 while (!OSCCTRL->STATUS.bit.OSC48MRDY) { in osc48m_init()
Dsoc_samd5x.c29 while (!OSC32KCTRL->STATUS.bit.XOSC32KRDY) { in osc32k_init()
52 OSCCTRL->Dpll[n].DPLLCTRLA.bit.ENABLE = 0; in dpll_init()
73 while (!(OSCCTRL->Dpll[n].DPLLSTATUS.bit.CLKRDY && in dpll_init()
74 OSCCTRL->Dpll[n].DPLLSTATUS.bit.LOCK)) { in dpll_init()
90 while (!OSCCTRL->STATUS.bit.DFLLRDY) { in dfll_init()
96 GCLK->CTRLA.bit.SWRST = 1; in gclk_reset()
97 while (GCLK->SYNCBUSY.bit.SWRST) { in gclk_reset()
127 CMCC->CTRL.bit.CEN = 0; in z_arm_platform_init()
Dsoc_port.c26 pg->PMUX[idx].bit.PMUXO = func; in soc_port_pinmux_set()
28 pg->PMUX[idx].bit.PMUXE = func; in soc_port_pinmux_set()
30 pg->PINCFG[pin].bit.PMUXEN = 1; in soc_port_pinmux_set()
57 pincfg.bit.PULLEN = 1; in soc_port_configure()
61 pincfg.bit.INEN = 1; in soc_port_configure()
69 pincfg.bit.DRVSTR = 1; in soc_port_configure()
/Zephyr-Core-3.7.0/drivers/usb/device/
Dusb_dc_sam0.c176 regs->PADCAL.bit.TRANSN = pad_transn; in usb_sam0_load_padcal()
191 regs->PADCAL.bit.TRANSP = pad_transp; in usb_sam0_load_padcal()
206 regs->PADCAL.bit.TRIM = pad_trim; in usb_sam0_load_padcal()
226 MCLK->APBBMASK.bit.USB_ = 1; in usb_dc_attach()
236 PM->APBBMASK.bit.USB_ = 1; in usb_dc_attach()
242 while (GCLK->STATUS.bit.SYNCBUSY) { in usb_dc_attach()
247 regs->CTRLA.bit.SWRST = 1; in usb_dc_attach()
253 regs->QOSCTRL.bit.CQOS = 2; in usb_dc_attach()
254 regs->QOSCTRL.bit.DQOS = 2; in usb_dc_attach()
286 regs->CTRLA.bit.ENABLE = 1; in usb_dc_attach()
[all …]
/Zephyr-Core-3.7.0/modules/lvgl/
Dlvgl_display_mono.c58 uint8_t bit; in lvgl_set_px_cb_mono() local
64 bit = 7 - y % 8; in lvgl_set_px_cb_mono()
66 bit = y % 8; in lvgl_set_px_cb_mono()
72 bit = 7 - x % 8; in lvgl_set_px_cb_mono()
74 bit = x % 8; in lvgl_set_px_cb_mono()
80 *buf_xy &= ~BIT(bit); in lvgl_set_px_cb_mono()
82 *buf_xy |= BIT(bit); in lvgl_set_px_cb_mono()
86 *buf_xy |= BIT(bit); in lvgl_set_px_cb_mono()
88 *buf_xy &= ~BIT(bit); in lvgl_set_px_cb_mono()
/Zephyr-Core-3.7.0/drivers/display/
DKconfig.stm32_ltdc27 One pixel consists of 8-bit alpha, 8-bit red, 8-bit green and 8-bit blue value
33 One pixel consists of 8-bit red, 8-bit green and 8-bit blue value
39 One pixel consists of 5-bit red, 6-bit green and 5-bit blue value
/Zephyr-Core-3.7.0/drivers/watchdog/
Dwdt_sam0.c32 #define WDT_SYNCBUSY WDT_REGS->STATUS.bit.SYNCBUSY
54 WDT_REGS->CTRLA.bit.ENABLE = on; in wdt_sam0_set_enable()
56 WDT_REGS->CTRL.bit.ENABLE = on; in wdt_sam0_set_enable()
63 return WDT_REGS->CTRLA.bit.ENABLE; in wdt_sam0_is_enabled()
65 return WDT_REGS->CTRL.bit.ENABLE; in wdt_sam0_is_enabled()
181 WDT_REGS->CTRLA.bit.WEN = 1; in wdt_sam0_install_timeout()
183 WDT_REGS->CTRL.bit.WEN = 1; in wdt_sam0_install_timeout()
193 WDT_REGS->EWCTRL.bit.EWOFFSET = per - 1U; in wdt_sam0_install_timeout()
197 WDT_REGS->CTRLA.bit.WEN = 0; in wdt_sam0_install_timeout()
199 WDT_REGS->CTRL.bit.WEN = 0; in wdt_sam0_install_timeout()
[all …]
/Zephyr-Core-3.7.0/soc/nuvoton/npcx/common/
Dsoc_dt.h66 .bit = DT_PHA(DT_DRV_INST(inst), clocks, bit), \
80 .bit = DT_CLOCKS_CELL_BY_IDX(DT_DRV_INST(inst), i, bit), \
94 .bit = DT_CLOCKS_CELL_BY_NAME(DT_DRV_INST(inst), name, bit), \
165 .bit = DT_PHA(NPCX_DT_PHANDLE_FROM_WUI_NAME(inst, name), miwus, \
166 bit), \
192 .bit = DT_PHA(NPCX_DT_PHANDLE_FROM_WUI_MAPS(inst, i), miwus, bit), \
312 .bit = DT_PHA(NPCX_DT_PHANDLE_VW_WUI(name), miwus, bit), \
378 .bit = DT_PHA(DT_PROP_BY_IDX(node_id, prop, idx), lvols, bit), \
/Zephyr-Core-3.7.0/drivers/pinctrl/renesas/rcar/
Dpfc_rcar.c79 uint8_t bit = pin % 32; in pfc_rcar_set_gpsr() local
84 val |= BIT(bit); in pfc_rcar_set_gpsr()
86 val &= ~BIT(bit); in pfc_rcar_set_gpsr()
158 uint8_t *bit) in pfc_rcar_get_bias_reg() argument
166 *bit = i; in pfc_rcar_get_bias_reg()
179 uint8_t bit; in pfc_rcar_set_bias() local
180 const struct pfc_bias_reg *bias_reg = pfc_rcar_get_bias_reg(pin, &bit); in pfc_rcar_set_bias()
189 sys_write32(val & ~BIT(bit), pfc_base + bias_reg->puen); in pfc_rcar_set_bias()
192 sys_write32(val | BIT(bit), pfc_base + bias_reg->puen); in pfc_rcar_set_bias()
197 sys_write32(val | BIT(bit), pfc_base + bias_reg->pud); in pfc_rcar_set_bias()
[all …]
/Zephyr-Core-3.7.0/drivers/interrupt_controller/
Dintc_miwu.c110 if (BIT(cb->io_cb.params.wui.bit) & mask) { in intc_miwu_dispatch_isr()
118 if (BIT(cb->dev_cb.params.wui.bit) & mask) { in intc_miwu_dispatch_isr()
129 static void npcx_miwu_set_pseudo_both_edge(uint8_t table, uint8_t group, uint8_t bit) in npcx_miwu_set_pseudo_both_edge() argument
133 uint8_t pmask = BIT(bit); in npcx_miwu_set_pseudo_both_edge()
135 if (IS_BIT_SET(NPCX_WKST(base, group), bit)) { in npcx_miwu_set_pseudo_both_edge()
190 NPCX_WKEN(base, wui->group) |= BIT(wui->bit); in npcx_miwu_irq_enable()
193 if ((data->both_edge_pins[wui->group] & BIT(wui->bit)) != 0) { in npcx_miwu_irq_enable()
194 npcx_miwu_set_pseudo_both_edge(wui->table, wui->group, wui->bit); in npcx_miwu_irq_enable()
205 NPCX_WKEN(base, wui->group) &= ~BIT(wui->bit); in npcx_miwu_irq_disable()
213 NPCX_WKINEN(base, wui->group) |= BIT(wui->bit); in npcx_miwu_io_enable()
[all …]
/Zephyr-Core-3.7.0/drivers/dma/
Ddma_sam0.c124 DMA_REGS->CHCTRLB.bit.LVL = config->channel_priority; in dma_sam0_config()
162 chcfg->CHPRILVL.bit.PRILVL = config->channel_priority; in dma_sam0_config()
199 btctrl.bit.BEATSIZE = DMAC_BTCTRL_BEATSIZE_BYTE_Val; in dma_sam0_config()
202 btctrl.bit.BEATSIZE = DMAC_BTCTRL_BEATSIZE_HWORD_Val; in dma_sam0_config()
205 btctrl.bit.BEATSIZE = DMAC_BTCTRL_BEATSIZE_WORD_Val; in dma_sam0_config()
220 btctrl.bit.SRCINC = 1; in dma_sam0_config()
233 btctrl.bit.DSTINC = 1; in dma_sam0_config()
243 btctrl.bit.VALID = 1; in dma_sam0_config()
274 if (DMA_REGS->CHCTRLB.bit.TRIGSRC == 0) { in dma_sam0_start()
282 chcfg->CHCTRLA.bit.ENABLE = 1; in dma_sam0_start()
[all …]
/Zephyr-Core-3.7.0/drivers/dac/
Ddac_sam0.c89 regs->CTRLA.bit.SWRST = 1; in dac_sam0_init()
90 while (regs->STATUS.bit.SYNCBUSY) { in dac_sam0_init()
93 regs->CTRLB.bit.REFSEL = cfg->refsel; in dac_sam0_init()
94 regs->CTRLB.bit.EOEN = 1; in dac_sam0_init()
97 regs->CTRLA.bit.ENABLE = 1; in dac_sam0_init()
98 while (regs->STATUS.bit.SYNCBUSY) { in dac_sam0_init()
118 .pm_apbc_bit = DT_INST_CLOCKS_CELL_BY_NAME(n, pm, bit), \

12345678910>>...28