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Searched refs:_sw_isr_table (Results 1 – 25 of 48) sorted by relevance

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/Zephyr-Core-3.7.0/soc/cdns/xtensa_sample_controller/include/
D_soc_inthandlers.h93 struct _isr_table_entry *e = &_sw_isr_table[0]; in _xtensa_handle_one_int1()
99 struct _isr_table_entry *e = &_sw_isr_table[1]; in _xtensa_handle_one_int1()
105 struct _isr_table_entry *e = &_sw_isr_table[2]; in _xtensa_handle_one_int1()
113 struct _isr_table_entry *e = &_sw_isr_table[3]; in _xtensa_handle_one_int1()
119 struct _isr_table_entry *e = &_sw_isr_table[4]; in _xtensa_handle_one_int1()
126 struct _isr_table_entry *e = &_sw_isr_table[5]; in _xtensa_handle_one_int1()
132 struct _isr_table_entry *e = &_sw_isr_table[6]; in _xtensa_handle_one_int1()
142 struct _isr_table_entry *e = &_sw_isr_table[7]; in _xtensa_handle_one_int1()
148 struct _isr_table_entry *e = &_sw_isr_table[15]; in _xtensa_handle_one_int1()
154 struct _isr_table_entry *e = &_sw_isr_table[16]; in _xtensa_handle_one_int1()
[all …]
/Zephyr-Core-3.7.0/soc/intel/intel_adsp/ace/
D_soc_inthandlers.h64 _sw_isr_table[irq].isr(_sw_isr_table[irq].arg); in _xtensa_handle_one_int1()
89 _sw_isr_table[irq].isr(_sw_isr_table[irq].arg); in _xtensa_handle_one_int2()
114 _sw_isr_table[irq].isr(_sw_isr_table[irq].arg); in _xtensa_handle_one_int3()
124 _sw_isr_table[8].isr(_sw_isr_table[8].arg); in _xtensa_handle_one_int5()
/Zephyr-Core-3.7.0/tests/kernel/interrupt/src/
Ddynamic_isr.c23 extern struct _isr_table_entry _sw_isr_table[];
49 if (_sw_isr_table[i].isr == z_irq_spurious) { in ZTEST()
54 zassert_true(_sw_isr_table[i].isr == z_irq_spurious, in ZTEST()
64 zassert_true(_sw_isr_table[i + IRQ_OFFSET].isr == dyn_isr && in ZTEST()
65 _sw_isr_table[i + IRQ_OFFSET].arg == argval, in ZTEST()
Ddynamic_shared_irq.c58 if (_sw_isr_table[table_idx].isr == &z_irq_spurious) { in get_irq_slot()
113 zassert_true(_sw_isr_table[fixture.irq1_table_idx + TABLE_OFFSET].isr == test_isr_0, in dynamic_shared_irq_suite_before()
115 zassert_true(!_sw_isr_table[fixture.irq1_table_idx + TABLE_OFFSET].arg, in dynamic_shared_irq_suite_before()
123 zassert_true(_sw_isr_table[fixture.irq1_table_idx + TABLE_OFFSET].isr == z_shared_isr, in dynamic_shared_irq_suite_before()
125 zassert_true(_sw_isr_table[fixture.irq1_table_idx + TABLE_OFFSET].arg == in dynamic_shared_irq_suite_before()
141 zassert_true(_sw_isr_table[fixture.irq2_table_idx + TABLE_OFFSET].isr == test_isr_2, in dynamic_shared_irq_suite_before()
143 zassert_true(_sw_isr_table[fixture.irq2_table_idx + TABLE_OFFSET].arg == (void *)2, in dynamic_shared_irq_suite_before()
202 zassert_true(_sw_isr_table[fixture.irq1_table_idx + TABLE_OFFSET].isr == test_isr_1, in ZTEST()
204 zassert_true(_sw_isr_table[fixture.irq1_table_idx + TABLE_OFFSET].arg == (void *)1, in ZTEST()
Dstatic_shared_irq.c42 zassert_true(_sw_isr_table[GIC_IRQ1].isr == z_shared_isr, in ZTEST()
44 zassert_true(_sw_isr_table[GIC_IRQ2].isr == test_isr_2, in ZTEST()
47 zassert_true(_sw_isr_table[GIC_IRQ1].arg == in ZTEST()
50 zassert_true(_sw_isr_table[GIC_IRQ2].arg == (void *)2, in ZTEST()
/Zephyr-Core-3.7.0/soc/intel/intel_adsp/cavs/
D_soc_inthandlers.h114 _sw_isr_table[irq].isr(_sw_isr_table[irq].arg); in _xtensa_handle_one_int1()
147 _sw_isr_table[irq].isr(_sw_isr_table[irq].arg); in _xtensa_handle_one_int2()
180 _sw_isr_table[irq].isr(_sw_isr_table[irq].arg); in _xtensa_handle_one_int3()
205 _sw_isr_table[irq].isr(_sw_isr_table[irq].arg); in _xtensa_handle_one_int4()
243 _sw_isr_table[irq].isr(_sw_isr_table[irq].arg); in _xtensa_handle_one_int5()
258 _sw_isr_table[irq].isr(_sw_isr_table[irq].arg); in _xtensa_handle_one_int7()
Dirq.c186 _sw_isr_table[table_idx].arg = parameter; in z_soc_irq_connect_dynamic()
187 _sw_isr_table[table_idx].isr = routine; in z_soc_irq_connect_dynamic()
/Zephyr-Core-3.7.0/soc/nxp/imx/imx8/adsp/
D_soc_inthandlers.h97 _sw_isr_table[irq].isr(_sw_isr_table[irq].arg); in _xtensa_handle_one_int1()
115 _sw_isr_table[irq].isr(_sw_isr_table[irq].arg); in _xtensa_handle_one_int2()
140 _sw_isr_table[irq].isr(_sw_isr_table[irq].arg); in _xtensa_handle_one_int3()
155 _sw_isr_table[irq].isr(_sw_isr_table[irq].arg); in _xtensa_handle_one_int5()
/Zephyr-Core-3.7.0/soc/nxp/imx/imx8m/adsp/
D_soc_inthandlers.h97 _sw_isr_table[irq].isr(_sw_isr_table[irq].arg); in _xtensa_handle_one_int1()
115 _sw_isr_table[irq].isr(_sw_isr_table[irq].arg); in _xtensa_handle_one_int2()
140 _sw_isr_table[irq].isr(_sw_isr_table[irq].arg); in _xtensa_handle_one_int3()
155 _sw_isr_table[irq].isr(_sw_isr_table[irq].arg); in _xtensa_handle_one_int5()
/Zephyr-Core-3.7.0/soc/nxp/imx/imx8x/adsp/
D_soc_inthandlers.h97 _sw_isr_table[irq].isr(_sw_isr_table[irq].arg); in _xtensa_handle_one_int1()
115 _sw_isr_table[irq].isr(_sw_isr_table[irq].arg); in _xtensa_handle_one_int2()
140 _sw_isr_table[irq].isr(_sw_isr_table[irq].arg); in _xtensa_handle_one_int3()
155 _sw_isr_table[irq].isr(_sw_isr_table[irq].arg); in _xtensa_handle_one_int5()
/Zephyr-Core-3.7.0/soc/espressif/common/include/
D_soc_inthandlers.h219 _sw_isr_table[irq].isr(_sw_isr_table[irq].arg); in _xtensa_handle_one_int1()
262 _sw_isr_table[irq].isr(_sw_isr_table[irq].arg); in _xtensa_handle_one_int3()
277 _sw_isr_table[irq].isr(_sw_isr_table[irq].arg); in _xtensa_handle_one_int7()
302 _sw_isr_table[irq].isr(_sw_isr_table[irq].arg); in _xtensa_handle_one_int5()
327 _sw_isr_table[irq].isr(_sw_isr_table[irq].arg); in _xtensa_handle_one_int2()
360 _sw_isr_table[irq].isr(_sw_isr_table[irq].arg); in _xtensa_handle_one_int4()
/Zephyr-Core-3.7.0/arch/common/
Ddynamic_isr.c31 _sw_isr_table[table_idx].arg = param; in z_isr_install()
32 _sw_isr_table[table_idx].isr = routine; in z_isr_install()
Dshared_irq.c58 entry = &_sw_isr_table[table_idx]; in z_isr_install()
139 _sw_isr_table[table_idx].isr = shared_entry->clients[0].isr; in shared_irq_remove_client()
140 _sw_isr_table[table_idx].arg = shared_entry->clients[0].arg; in shared_irq_remove_client()
178 entry = &_sw_isr_table[table_idx]; in z_isr_uninstall()
Disr_tables.c91 struct _isr_table_entry __sw_isr_table _sw_isr_table[IRQ_TABLE_SIZE] = { variable
/Zephyr-Core-3.7.0/arch/sparc/core/
Dirq_manage.c36 ite = &_sw_isr_table[irl]; in z_sparc_enter_irq()
44 ite = &_sw_isr_table[irl]; in z_sparc_enter_irq()
/Zephyr-Core-3.7.0/soc/nxp/imxrt/imxrt5xx/f1/include/
D_soc_inthandlers.h130 _sw_isr_table[irq].isr(_sw_isr_table[irq].arg); in _xtensa_handle_one_int1()
148 _sw_isr_table[irq].isr(_sw_isr_table[irq].arg); in _xtensa_handle_one_int2()
166 _sw_isr_table[irq].isr(_sw_isr_table[irq].arg); in _xtensa_handle_one_int3()
186 _sw_isr_table[irq].isr(_sw_isr_table[irq].arg); in _xtensa_handle_one_int5()
/Zephyr-Core-3.7.0/drivers/interrupt_controller/
Dintc_renesas_ra_icu.c51 if (_sw_isr_table[i].isr == z_irq_spurious) { in ra_icu_query_available_irq()
71 *cb = _sw_isr_table[irq].isr; in ra_icu_query_irq_config()
72 *cbarg = (void *)_sw_isr_table[irq].arg; in ra_icu_query_irq_config()
Dintc_mtk_adsp.c48 _sw_isr_table[off].isr(_sw_isr_table[off].arg); in intc_isr()
Dintc_dw.c34 _sw_isr_table[intr_offset].isr( in dw_ictl_dispatch_child_isrs()
35 _sw_isr_table[intr_offset].arg); in dw_ictl_dispatch_child_isrs()
DKconfig.multilevel45 int "Offset in _sw_isr_table for level 2 interrupts"
49 This is the offset in _sw_isr_table, the generated ISR handler table,
109 int "Offset in _sw_isr_table for level 3 interrupts"
113 This is the offset in _sw_isr_table, the generated ISR handler table,
Dintc_cavs.c49 _sw_isr_table[intr_offset].isr( in cavs_ictl_dispatch_child_isrs()
50 _sw_isr_table[intr_offset].arg); in cavs_ictl_dispatch_child_isrs()
/Zephyr-Core-3.7.0/soc/nxp/imx/imx8ulp/adsp/
D_soc_inthandlers.h130 _sw_isr_table[irq].isr(_sw_isr_table[irq].arg); in _xtensa_handle_one_int5()
199 _sw_isr_table[irq].isr(_sw_isr_table[irq].arg); in _xtensa_handle_one_int2()
273 _sw_isr_table[irq].isr(_sw_isr_table[irq].arg); in _xtensa_handle_one_int3()
342 _sw_isr_table[irq].isr(_sw_isr_table[irq].arg); in _xtensa_handle_one_int1()
/Zephyr-Core-3.7.0/arch/arm/core/cortex_m/
Disr_wrapper.c76 struct _isr_table_entry *entry = &_sw_isr_table[irq_number]; in _isr_wrapper()
/Zephyr-Core-3.7.0/arch/arm64/core/
Disr_wrapper.S21 GDATA(_sw_isr_table)
88 ldr x1, =_sw_isr_table
/Zephyr-Core-3.7.0/arch/arm/core/cortex_a_r/
Disr_wrapper.S30 GDATA(_sw_isr_table)
207 ldr r1, =_sw_isr_table
308 ldr r1, =_sw_isr_table

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