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Searched refs:CTRL (Results 1 – 25 of 135) sorted by relevance

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/Zephyr-latest/drivers/watchdog/
Dwdt_rts5912.c49 wdt_reg->CTRL |= WDT_CTRL_CLRRSTFLAG; in wdt_rts5912_isr()
67 if (wdt_reg->CTRL & WDT_CTRL_EN) { in wdt_rts5912_setup()
85 wdt_reg->CTRL |= (WDT_CTRL_CLRRSTFLAG | WDT_CTRL_RELOAD); in wdt_rts5912_setup()
86 wdt_reg->CTRL |= WDT_CTRL_EN; in wdt_rts5912_setup()
99 if (!(wdt_reg->CTRL & WDT_CTRL_EN)) { in wdt_rts5912_disable()
104 wdt_reg->CTRL |= WDT_CTRL_CLRRSTFLAG; in wdt_rts5912_disable()
105 wdt_reg->CTRL &= ~WDT_CTRL_EN; in wdt_rts5912_disable()
126 if (wdt_reg->CTRL & WDT_CTRL_EN) { in wdt_rts5912_install_timeout()
139 wdt_reg->CTRL |= WDT_CTRL_RSTEN; in wdt_rts5912_install_timeout()
142 wdt_reg->CTRL &= ~WDT_CTRL_RSTEN; in wdt_rts5912_install_timeout()
[all …]
Dwdt_mchp_xec.c40 if (regs->CTRL & MCHP_WDT_CTRL_EN) { in wdt_xec_setup()
55 regs->CTRL |= MCHP_WDT_CTRL_JTAG_STALL_EN; in wdt_xec_setup()
57 regs->CTRL &= ~MCHP_WDT_CTRL_JTAG_STALL_EN; in wdt_xec_setup()
60 regs->CTRL |= MCHP_WDT_CTRL_EN; in wdt_xec_setup()
73 if (!(regs->CTRL & MCHP_WDT_CTRL_EN)) { in wdt_xec_disable()
77 regs->CTRL &= ~MCHP_WDT_CTRL_EN; in wdt_xec_disable()
92 if (regs->CTRL & MCHP_WDT_CTRL_EN) { in wdt_xec_install_timeout()
105 regs->CTRL |= MCHP_WDT_CTRL_MODE_IRQ; in wdt_xec_install_timeout()
113 regs->CTRL &= ~MCHP_WDT_CTRL_MODE_IRQ; in wdt_xec_install_timeout()
138 if (!(regs->CTRL & MCHP_WDT_CTRL_EN)) { in wdt_xec_feed()
Dwdt_sam4l.c73 wdt->CTRL = WDT_CTRL_KEY(WDT_FIRST_KEY) in wdt_sam4l_set_ctrl()
75 wdt->CTRL = WDT_CTRL_KEY(WDT_SECOND_KEY) in wdt_sam4l_set_ctrl()
160 reg = wdt->CTRL; in wdt_sam4l_setup()
177 reg = wdt->CTRL in wdt_sam4l_setup()
182 while ((wdt->CTRL & WDT_CTRL_EN) != WDT_CTRL_EN) { in wdt_sam4l_setup()
193 if (wdt->CTRL & WDT_CTRL_SFV) { in wdt_sam4l_disable()
198 wdt_sam4l_set_ctrl(cfg, wdt->CTRL & ~WDT_CTRL_EN); in wdt_sam4l_disable()
199 while (wdt->CTRL & WDT_CTRL_EN) { in wdt_sam4l_disable()
202 wdt_sam4l_set_ctrl(cfg, wdt->CTRL & ~WDT_CTRL_CEN); in wdt_sam4l_disable()
203 while (wdt->CTRL & WDT_CTRL_CEN) { in wdt_sam4l_disable()
[all …]
Dwdt_sam0.c56 WDT_REGS->CTRL.bit.ENABLE = on; in wdt_sam0_set_enable()
65 return WDT_REGS->CTRL.bit.ENABLE; in wdt_sam0_is_enabled()
183 WDT_REGS->CTRL.bit.WEN = 1; in wdt_sam0_install_timeout()
199 WDT_REGS->CTRL.bit.WEN = 0; in wdt_sam0_install_timeout()
/Zephyr-latest/drivers/counter/
Dcounter_mchp_xec.c65 if (counter->CTRL & MCHP_BTMR_CTRL_ENABLE) { in counter_xec_start()
69 counter->CTRL |= (MCHP_BTMR_CTRL_ENABLE | MCHP_BTMR_CTRL_START); in counter_xec_start()
81 if (!(counter->CTRL & MCHP_BTMR_CTRL_ENABLE)) { in counter_xec_stop()
86 reg = counter->CTRL; in counter_xec_stop()
92 counter->CTRL = reg; in counter_xec_stop()
149 counter->CTRL |= MCHP_BTMR_CTRL_START; in counter_xec_set_alarm()
165 counter->CTRL &= ~MCHP_BTMR_CTRL_START; in counter_xec_cancel_alarm()
207 restart = ((counter->CTRL & MCHP_BTMR_CTRL_START) != 0U); in counter_xec_set_top_value()
209 counter->CTRL &= ~MCHP_BTMR_CTRL_START; in counter_xec_set_top_value()
230 counter->CTRL |= MCHP_BTMR_CTRL_AUTO_RESTART; in counter_xec_set_top_value()
[all …]
/Zephyr-latest/drivers/timer/
Dmchp_xec_rtos_timer.c141 TIMER_REGS->CTRL = 0U; in timer_restart()
142 TIMER_REGS->CTRL = MCHP_RTMR_CTRL_BLK_EN; in timer_restart()
144 TIMER_REGS->CTRL = TIMER_START_VAL; in timer_restart()
163 if ((ccr == 0) && (TIMER_REGS->CTRL & MCHP_RTMR_CTRL_START)) { in timer_count()
200 TIMER_REGS->CTRL = 0U; /* stop timer */ in sys_clock_set_timeout()
220 TIMER_REGS->CTRL = 0u; in sys_clock_set_timeout()
368 TIMER_REGS->CTRL = 0U; in sys_clock_disable()
408 TIMER_REGS->CTRL = 0u; in sys_clock_driver_init()
428 BTMR32_0_REGS->CTRL = MCHP_BTMR_CTRL_SOFT_RESET; in sys_clock_driver_init()
429 BTMR32_0_REGS->CTRL = btmr_ctrl; in sys_clock_driver_init()
[all …]
Drealtek_rts5912_rtmr.c52 RTMR_REG->CTRL = 0ul; in rtmr_restart()
54 RTMR_REG->CTRL = RTOSTMR_CTRL_INTEN_Msk | RTOSTMR_CTRL_EN_Msk; in rtmr_restart()
61 if ((counter == 0) && (RTMR_REG->CTRL & RTOSTMR_CTRL_EN_Msk)) { in rtmr_get_counter()
109 RTMR_REG->CTRL = 0U; in sys_clock_set_timeout()
128 RTMR_REG->CTRL = 0U; in sys_clock_set_timeout()
182 RTMR_REG->CTRL = 0ul; in sys_clock_disable()
245 SLWTMR_REG->CTRL = RTOSTMR_CTRL_MDSEL_Msk | RTOSTMR_CTRL_EN_Msk; in sys_clock_driver_init()
Dsam0_rtc_timer.c128 RTC0->CTRL.reg &= ~RTC_MODE0_CTRL_ENABLE; in rtc_reset()
137 RTC0->CTRL.bit.SWRST = 1; in rtc_reset()
138 while (RTC0->CTRL.bit.SWRST) { in rtc_reset()
302 RTC0->CTRL.reg = ctrl; in sys_clock_driver_init()
322 RTC0->CTRL.reg |= RTC_MODE0_CTRL_ENABLE; in sys_clock_driver_init()
Dcortex_m_systick.c183 uint32_t ctrl = SysTick->CTRL; /* B */ in elapsed()
222 (void)SysTick->CTRL; in elapsed()
305 SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; in sys_clock_set_timeout()
513 SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk; in sys_clock_idle_exit()
520 SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; in sys_clock_disable()
531 SysTick->CTRL |= (SysTick_CTRL_ENABLE_Msk | in sys_clock_driver_init()
/Zephyr-latest/soc/microchip/mec/mec15xx/
Dtiming.c16 B32TMR1_REGS->CTRL = MCHP_BTMR_CTRL_ENABLE | in soc_timing_init()
29 B32TMR1_REGS->CTRL |= MCHP_BTMR_CTRL_START; in soc_timing_start()
34 B32TMR1_REGS->CTRL &= ~MCHP_BTMR_CTRL_START; in soc_timing_stop()
Ddevice_power.c127 (uintptr_t)&B16TMR0_REGS->CTRL, 0
130 (uintptr_t)&B16TMR1_REGS->CTRL, 0
133 (uintptr_t)&B32TMR0_REGS->CTRL, 0
136 (uintptr_t)&B32TMR1_REGS->CTRL, 0
139 (uintptr_t)&CCT_REGS->CTRL,
/Zephyr-latest/soc/microchip/mec/mec172x/
Dtiming.c27 regs->CTRL = MCHP_BTMR_CTRL_ENABLE | MCHP_BTMR_CTRL_AUTO_RESTART | in soc_timing_init()
39 regs->CTRL |= MCHP_BTMR_CTRL_START; in soc_timing_start()
44 regs->CTRL &= ~MCHP_BTMR_CTRL_START; in soc_timing_stop()
Dsoc_power_debug.h27 regs->CTRL[DP_GPIO_ID] = gpio_ctrl_val; in pm_dp_gpio()
/Zephyr-latest/arch/arm/include/cortex_m/
Ddwt.h101 DWT->CTRL |= DWT_CTRL_CYCCNTENA_Msk; in z_arm_dwt_init_cycle_counter()
106 __ASSERT((DWT->CTRL & DWT_CTRL_NOCYCCNT_Msk) == 0, "DWT implements no cycle counter. " in z_arm_dwt_init_cycle_counter()
132 DWT->CTRL |= DWT_CTRL_CYCCNTENA_Msk; in z_arm_dwt_cycle_count_start()
/Zephyr-latest/drivers/pinctrl/
Dpinctrl_mchp_xec.c108 regs->CTRL[idx] &= ~(BIT(MCHP_GPIO_CTRL_AOD_POS) | BIT(MCHP_GPIO_CTRL_INPAD_DIS_POS)); in xec_config_pin()
109 pcr1 = regs->CTRL[idx]; /* current configuration including pin input state */ in xec_config_pin()
110 pcr1 = regs->CTRL[idx]; /* read multiple times to allow propagation from pad */ in xec_config_pin()
111 pcr1 = regs->CTRL[idx]; /* Is this necessary? */ in xec_config_pin()
159 regs->CTRL[idx] = pcr1; in xec_config_pin()
161 regs->CTRL[idx] = pcr1 | BIT(MCHP_GPIO_CTRL_AOD_POS); in xec_config_pin()
/Zephyr-latest/drivers/ps2/
Dps2_mchp_xec.c133 regs->CTRL = MCHP_PS2_CTRL_EN_POS; in ps2_xec_configure()
179 regs->CTRL = 0x00; in ps2_xec_write()
187 regs->CTRL = MCHP_PS2_CTRL_TR_TX | MCHP_PS2_CTRL_EN; in ps2_xec_write()
207 regs->CTRL = 0x00; in ps2_xec_inhibit_interface()
224 regs->CTRL = MCHP_PS2_CTRL_EN; in ps2_xec_enable_interface()
257 regs->CTRL |= MCHP_PS2_CTRL_EN; in ps2_xec_pm_action()
277 regs->CTRL &= ~MCHP_PS2_CTRL_EN; in ps2_xec_pm_action()
311 regs->CTRL = 0x00; in ps2_xec_isr()
337 regs->CTRL = MCHP_PS2_CTRL_EN; in ps2_xec_isr()
/Zephyr-latest/tests/benchmarks/cmsis_dsp/common/
Dbenchmark_common.h27 DWT->CTRL |= DWT_CTRL_CYCCNTENA_Msk; in benchmark_begin()
33 DWT->CTRL &= ~DWT_CTRL_CYCCNTENA_Msk; in benchmark_end()
/Zephyr-latest/soc/microchip/mec/common/reg/
Dmec_timers.h82 volatile uint32_t CTRL; member
109 volatile uint16_t CTRL; member
140 volatile uint32_t CTRL; member
182 volatile uint32_t CTRL; member
261 volatile uint32_t CTRL; member
Dmec_gpio.h17 volatile uint32_t CTRL[174]; member
/Zephyr-latest/soc/microchip/mec/common/
Dsoc_i2c.c82 if (regs->CTRL[idx_scl] & BIT(MCHP_GPIO_CTRL_INPAD_VAL_POS)) { in soc_i2c_port_lines_get()
85 if (regs->CTRL[idx_sda] & BIT(MCHP_GPIO_CTRL_INPAD_VAL_POS)) { in soc_i2c_port_lines_get()
/Zephyr-latest/arch/arm/core/cortex_m/
Ddebug.c75 if (((DWT->CTRL & DWT_CTRL_NUMCOMP_Msk) >> DWT_CTRL_NUMCOMP_Pos) < 2) { in z_arm_debug_enable_null_pointer_detection()
93 if (((DWT->CTRL & DWT_CTRL_NUMCOMP_Msk) >> DWT_CTRL_NUMCOMP_Pos) < 1) { in z_arm_debug_enable_null_pointer_detection()
/Zephyr-latest/drivers/rtc/
Drtc_nxp_irtc.c92 irtc_reg->CTRL |= RTC_CTRL_DST_EN(timeptr->tm_isdst); in nxp_irtc_set_time()
119 ((irtc_reg->CTRL & RTC_CTRL_DST_EN_MASK) >> RTC_CTRL_DST_EN_SHIFT); in nxp_irtc_get_time()
189 irtc_reg->CTRL &= ~(0xC); in nxp_irtc_alarm_set_time()
192 irtc_reg->CTRL |= RTC_CTRL_ALM_MATCH(0x4); in nxp_irtc_alarm_set_time()
195 irtc_reg->CTRL |= RTC_CTRL_ALM_MATCH(0x8); in nxp_irtc_alarm_set_time()
198 irtc_reg->CTRL |= RTC_CTRL_ALM_MATCH(0xC); in nxp_irtc_alarm_set_time()
201 irtc_reg->CTRL |= RTC_CTRL_ALM_MATCH(0x0); in nxp_irtc_alarm_set_time()
332 irtc_reg->CTRL = RTC_CTRL_CLK_SEL(config->clock_src) | in nxp_irtc_init()
/Zephyr-latest/soc/nordic/nrf54h/
Dpm_s2ram.c40 uint32_t CTRL; member
88 backup->CTRL = MPU->CTRL; in mpu_suspend()
110 MPU->CTRL = backup->CTRL; in mpu_resume()
/Zephyr-latest/soc/realtek/ec/rts5912/reg/
Dreg_wdt.h15 volatile uint32_t CTRL; member
/Zephyr-latest/drivers/spi/
Dspi_xec_qmspi.c202 regs->CTRL = smode; in qmspi_configure()
253 ifm = regs->CTRL & MCHP_QMSPI_C_IFM_MASK; in qmspi_tx_dummy_clocks()
266 regs->CTRL |= MCHP_QMSPI_C_DESCR_EN; in qmspi_tx_dummy_clocks()
342 descr = (regs->CTRL & MCHP_QMSPI_C_IFM_MASK); in qmspi_descr_alloc()
414 regs->CTRL = (regs->CTRL & MCHP_QMSPI_C_IFM_MASK) | in qmspi_tx()
484 regs->CTRL = (regs->CTRL & MCHP_QMSPI_C_IFM_MASK) in qmspi_rx()

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