Home
last modified time | relevance | path

Searched refs:CR (Results 1 – 25 of 34) sorted by relevance

12

/Zephyr-Core-3.7.0/drivers/flash/
Dflash_stm32f2x.c62 if (regs->CR & FLASH_CR_LOCK) { in write_byte()
72 regs->CR &= ~FLASH_CR_PSIZE; in write_byte()
73 regs->CR |= FLASH_PSIZE_BYTE; in write_byte()
74 regs->CR |= FLASH_CR_PG; in write_byte()
77 tmp = regs->CR; in write_byte()
85 regs->CR &= (~FLASH_CR_PG); in write_byte()
97 if (regs->CR & FLASH_CR_LOCK) { in erase_sector()
107 regs->CR &= ~FLASH_CR_SNB; in erase_sector()
108 regs->CR |= FLASH_CR_SER | (sector << 3); in erase_sector()
109 regs->CR |= FLASH_CR_STRT; in erase_sector()
[all …]
Dflash_stm32g4x.c87 if (regs->CR & FLASH_CR_LOCK) { in write_dword()
121 regs->CR |= FLASH_CR_PG; in write_dword()
124 tmp = regs->CR; in write_dword()
134 regs->CR &= (~FLASH_CR_PG); in write_dword()
156 if (regs->CR & FLASH_CR_LOCK) { in erase_page()
174 regs->CR &= ~FLASH_CR_BKER_Msk; in erase_page()
179 regs->CR &= ~FLASH_CR_BKER_Msk; in erase_page()
184 regs->CR |= FLASH_CR_BKER; in erase_page()
189 regs->CR |= FLASH_CR_BKER; in erase_page()
202 regs->CR |= FLASH_CR_PER; in erase_page()
[all …]
Dflash_stm32l4x.c81 if (regs->CR & FLASH_CR_LOCK) { in write_dword()
114 regs->CR |= FLASH_CR_PG; in write_dword()
117 tmp = regs->CR; in write_dword()
127 regs->CR &= (~FLASH_CR_PG); in write_dword()
178 if (regs->CR & FLASH_CR_LOCK) { in erase_page()
191 regs->CR |= FLASH_CR_PER; in erase_page()
193 regs->CR &= ~FLASH_CR_BKER_Msk; in erase_page()
196 regs->CR |= FLASH_CR_BKER; in erase_page()
198 regs->CR &= ~FLASH_CR_PNB_Msk; in erase_page()
199 regs->CR |= ((page % pages_per_bank) << 3); in erase_page()
[all …]
Dflash_stm32wbx.c72 if (regs->CR & FLASH_CR_LOCK) { in write_dword()
160 regs->CR |= FLASH_CR_PG; in write_dword()
163 tmp = regs->CR; in write_dword()
197 regs->CR &= (~FLASH_CR_PG); in write_dword()
212 if (regs->CR & FLASH_CR_LOCK) { in erase_page()
296 regs->CR |= FLASH_CR_PER; in erase_page()
297 regs->CR &= ~FLASH_CR_PNB_Msk; in erase_page()
298 regs->CR |= page << FLASH_CR_PNB_Pos; in erase_page()
300 regs->CR |= FLASH_CR_STRT; in erase_page()
328 regs->CR &= ~FLASH_CR_PER; in erase_page()
Dflash_stm32g0x.c65 if (regs->CR & FLASH_CR_LOCK) { in write_dword()
87 regs->CR |= FLASH_CR_PG; in write_dword()
90 tmp = regs->CR; in write_dword()
100 regs->CR &= (~FLASH_CR_PG); in write_dword()
113 if (regs->CR & FLASH_CR_LOCK) { in erase_page()
130 tmp = regs->CR; in erase_page()
155 regs->CR = tmp; in erase_page()
160 regs->CR &= ~FLASH_CR_PER; in erase_page()
Dflash_stm32f4x.c93 if (regs->CR & FLASH_CR_LOCK) { in write_value()
113 regs->CR &= CR_PSIZE_MASK; in write_value()
114 regs->CR |= FLASH_PROGRAM_SIZE; in write_value()
115 regs->CR |= FLASH_CR_PG; in write_value()
118 tmp = regs->CR; in write_value()
123 regs->CR &= (~FLASH_CR_PG); in write_value()
144 if (regs->CR & FLASH_CR_LOCK) { in erase_sector()
171 regs->CR &= CR_PSIZE_MASK; in erase_sector()
172 regs->CR |= FLASH_PROGRAM_SIZE; in erase_sector()
174 regs->CR &= ~FLASH_CR_SNB; in erase_sector()
[all …]
Dflash_stm32f7x.c47 if (regs->CR & FLASH_CR_LOCK) { in write_byte()
57 regs->CR = (regs->CR & CR_PSIZE_MASK) | in write_byte()
68 regs->CR &= (~FLASH_CR_PG); in write_byte()
79 if (regs->CR & FLASH_CR_LOCK) { in erase_sector()
103 regs->CR = (regs->CR & ~(FLASH_CR_PSIZE | FLASH_CR_SNB)) | in erase_sector()
112 regs->CR &= ~(FLASH_CR_SER | FLASH_CR_SNB); in erase_sector()
Dflash_stm32f1x.c50 return !!(regs->CR & FLASH_CR_LOCK); in is_flash_locked()
55 regs->CR |= FLASH_CR_PG; in write_enable()
60 regs->CR &= (~FLASH_CR_PG); in write_disable()
66 regs->CR |= FLASH_CR_PER; in erase_page_begin()
72 regs->CR |= FLASH_CR_STRT; in erase_page_begin()
77 regs->CR &= ~FLASH_CR_PER; in erase_page_end()
Dflash_stm32.c283 regs->CR |= FLASH_CR_LOCK; in flash_stm32_write_protection()
285 if (regs->CR & FLASH_CR_LOCK) { in flash_stm32_write_protection()
341 regs->CR &= ~FLASH_CR_OPTWRE; in flash_stm32_option_bytes_lock()
342 } else if (!(regs->CR & FLASH_CR_OPTWRE)) { in flash_stm32_option_bytes_lock()
348 regs->CR |= FLASH_CR_OPTLOCK; in flash_stm32_option_bytes_lock()
349 } else if (regs->CR & FLASH_CR_OPTLOCK) { in flash_stm32_option_bytes_lock()
407 regs->CR |= FLASH_CR_LOCK; in flash_stm32_control_register_disable()
Dflash_stm32.h51 #define CR1 CR
/Zephyr-Core-3.7.0/subsys/bluetooth/controller/ll_sw/openisa/hal/RV32M1/
Dcntr.c29 RTC->CR |= RTC_CR_SWR_MASK; in cntr_init()
30 RTC->CR &= ~RTC_CR_SWR_MASK; in cntr_init()
39 RTC->CR |= (RTC_CR_CPS(1) | RTC_CR_OSCE(1)); in cntr_init()
/Zephyr-Core-3.7.0/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_core/src/
Dtest_stm32_clock_configuration.c94 if (READ_BIT(RCC->CR, RCC_CR_PLLON) == RCC_CR_PLLON) { in ZTEST()
114 zassert_true(READ_BIT(RCC->CR, RCC_CR_CSSON), "HSE CSS is not enabled"); in ZTEST()
116 zassert_false(READ_BIT(RCC->CR, RCC_CR_CSSON), "HSE CSS unexpectedly enabled"); in ZTEST()
/Zephyr-Core-3.7.0/tests/drivers/clock_control/stm32_clock_configuration/stm32h7_core/src/
Dtest_stm32_clock_configuration.c85 zassert_true(READ_BIT(RCC->CR, RCC_CR_CSSHSEON), "HSE CSS is not enabled"); in ZTEST()
87 zassert_false(READ_BIT(RCC->CR, RCC_CR_CSSHSEON), "HSE CSS unexpectedly enabled"); in ZTEST()
/Zephyr-Core-3.7.0/drivers/usb_c/tcpc/
Ducpd_stm32.c164 uint32_t cr = LL_UCPD_ReadReg(config->ucpd_port, CR); in ucpd_get_cc_enable_mask()
278 cr = LL_UCPD_ReadReg(config->ucpd_port, CR); in ucpd_set_vconn()
283 LL_UCPD_WriteReg(config->ucpd_port, CR, cr); in ucpd_set_vconn()
374 cr = LL_UCPD_ReadReg(config->ucpd_port, CR); in dead_battery()
382 LL_UCPD_WriteReg(config->ucpd_port, CR, cr); in dead_battery()
412 cr = LL_UCPD_ReadReg(config->ucpd_port, CR); in ucpd_set_cc()
434 LL_UCPD_WriteReg(config->ucpd_port, CR, cr); in ucpd_set_cc()
457 cr = LL_UCPD_ReadReg(config->ucpd_port, CR); in ucpd_cc_set_polarity()
475 LL_UCPD_WriteReg(config->ucpd_port, CR, cr); in ucpd_cc_set_polarity()
493 cr = LL_UCPD_ReadReg(config->ucpd_port, CR); in ucpd_set_rx_enable()
[all …]
/Zephyr-Core-3.7.0/subsys/net/lib/http/
Dhttp_parser.c263 #define CR '\r' macro
296 (ch == CR || ch == LF || ch == 9 || \
495 p_cr = (const char *)memchr(p, CR, limit); in header_states()
801 if (LIKELY(ch == CR || ch == LF)) { in parser_execute()
809 if (ch == CR || ch == LF) { in parser_execute()
860 case CR: in parser_execute()
996 if ((ch == CR) || (ch == LF)) { in parser_execute()
1012 case CR: in parser_execute()
1037 if (!status_mark && ((ch == CR) || (ch == LF))) { in parser_execute()
1049 if (ch == CR) { in parser_execute()
[all …]
/Zephyr-Core-3.7.0/drivers/i2c/
Di2c_sam4l_twim.c294 twim->CR = TWIM_CR_MEN; in i2c_start_xfer()
295 twim->CR = TWIM_CR_SWRST; in i2c_start_xfer()
296 twim->CR = TWIM_CR_MDIS; in i2c_start_xfer()
372 twim->CR = TWIM_CR_MEN; in i2c_start_xfer()
567 twim->CR = TWIM_CR_MEN; in i2c_sam_twim_initialize()
570 twim->CR |= TWIM_CR_SWRST; in i2c_sam_twim_initialize()
/Zephyr-Core-3.7.0/drivers/ethernet/
Deth_smsc91x_priv.h61 #define CR 0x0 macro
/Zephyr-Core-3.7.0/samples/subsys/console/getline/
DREADME.rst41 line does not include any special "end of line" characters (like LF, CR,
/Zephyr-Core-3.7.0/drivers/mdio/
Dmdio_nxp_enet_qos.c189 ENET_QOS_REG_PREP(MAC_MDIO_ADDRESS, CR, divider); in nxp_enet_qos_mdio_init()
/Zephyr-Core-3.7.0/drivers/clock_control/
Dclock_stm32_ll_h7.c946 sysclk = (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)
989 hsivalue = (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV) >>
1006 sysclk = (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV) >> RCC_CR_HSIDIV_Pos));
/Zephyr-Core-3.7.0/drivers/entropy/
Dentropy_stm32.c183 cur_nist_cfg = READ_BIT(rng->CR, in configure_rng()
198 MODIFY_REG(rng->CR, cur_nist_cfg, (desired_nist_cfg | RNG_CR_CONDRST)); in configure_rng()
/Zephyr-Core-3.7.0/tests/drivers/flash/stm32/src/
Dmain.c210 return regs->CR & FLASH_CR_LOCK; in flash_cr_locked()
/Zephyr-Core-3.7.0/drivers/pwm/
Dpwm_mcux_pwt.c214 if (config->base->CR & PWT_CR_LVL_MASK) { in mcux_pwt_isr()
/Zephyr-Core-3.7.0/samples/boards/96b_argonkey/microphone/
DREADME.rst92 .. note:: In case the character 0x0a is interpreted as NL and an 0x0d (CR) is added,
/Zephyr-Core-3.7.0/drivers/dma/
Ddma_mcux_edma.c443 LOG_DBG("DMA CR 0x%x", DEV_BASE(dev)->CR); in dma_mcux_edma_start()
571 LOG_DBG("DMA CR 0x%x", DEV_BASE(dev)->CR); in dma_mcux_edma_get_status()

12