Searched refs:sw (Results 1 – 25 of 35) sorted by relevance
12
| /Zephyr-Core-3.6.0/soc/riscv/openisa_rv32m1/ |
| D | soc_irq.S | 36 sw t1, 0x00(t0)
55 sw t0, __soc_esf_t_lpstart0_OFFSET(a0)
56 sw t1, __soc_esf_t_lpend0_OFFSET(a0)
57 sw t2, __soc_esf_t_lpcount0_OFFSET(a0)
61 sw t0, __soc_esf_t_lpstart1_OFFSET(a0)
62 sw t1, __soc_esf_t_lpend1_OFFSET(a0)
63 sw t2, __soc_esf_t_lpcount1_OFFSET(a0)
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| D | wdog.S | 49 sw t2, WDOG_CNT_OFFSET(t1)
55 sw t2, WDOG_CS_OFFSET(t1)
59 sw t2, WDOG_TOVAL_OFFSET(t1)
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| /Zephyr-Core-3.6.0/soc/riscv/andes_v5/ae350/ |
| D | soc_irq.S | 28 sw t0, __soc_esf_t_mxstatus_OFFSET(a0)
31 sw t1, __soc_esf_t_ucode_OFFSET(a0)
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| /Zephyr-Core-3.6.0/soc/riscv/telink_tlsr/tlsr951x/ |
| D | soc_irq.S | 32 sw t0, __soc_esf_t_mxstatus_OFFSET(a0)
35 sw t1, __soc_esf_t_ucode_OFFSET(a0)
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| D | start.S | 51 sw t0, 0(t2)
62 sw t0, 0(t2)
74 sw t0, 0(t2)
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| /Zephyr-Core-3.6.0/arch/riscv/core/ |
| D | userspace.S | 29 sw a5, 0(a2) # Init error value to 0
50 sw a4, 0(a2)
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| D | asm_macros.inc | 21 /* register-wide load/store based on lw/sw (XLEN = 32) */
28 sw \rs, \mem
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| D | reset.S | 71 sw t2, 0x00(t0)
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| D | isr.S | 404 sw t2, ___cpu_t_nested_OFFSET(s0)
457 sw t1, 0(sp)
520 sw t2, ___cpu_t_nested_OFFSET(s0)
582 sw t2, ___cpu_t_nested_OFFSET(s0)
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| D | fpu.S | 59 sw t0, __z_riscv_fp_context_t_fcsr_OFFSET(a0)
|
| /Zephyr-Core-3.6.0/modules/lvgl/ |
| D | CMakeLists.txt | 80 ${LVGL_DIR}/src/draw/sw/lv_draw_sw_arc.c
81 ${LVGL_DIR}/src/draw/sw/lv_draw_sw_blend.c
82 ${LVGL_DIR}/src/draw/sw/lv_draw_sw.c
83 ${LVGL_DIR}/src/draw/sw/lv_draw_sw_dither.c
84 ${LVGL_DIR}/src/draw/sw/lv_draw_sw_gradient.c
85 ${LVGL_DIR}/src/draw/sw/lv_draw_sw_img.c
86 ${LVGL_DIR}/src/draw/sw/lv_draw_sw_layer.c
87 ${LVGL_DIR}/src/draw/sw/lv_draw_sw_letter.c
88 ${LVGL_DIR}/src/draw/sw/lv_draw_sw_line.c
89 ${LVGL_DIR}/src/draw/sw/lv_draw_sw_polygon.c
[all …]
|
| /Zephyr-Core-3.6.0/drivers/clock_control/ |
| D | clock_control_numaker_scc.c | 110 #define LOG_OSC_SW(osc, sw) \ argument
111 if (sw == NUMAKER_SCC_CLKSW_ENABLE) { \
113 } else if (sw == NUMAKER_SCC_CLKSW_DISABLE) { \
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| /Zephyr-Core-3.6.0/soc/riscv/espressif_esp32/esp32c3/ |
| D | soc_irq.S | 15 sw ra, 0x00(sp)
|
| /Zephyr-Core-3.6.0/dts/common/nordic/ |
| D | nrf_common.dtsi | 39 sw_pwm: sw-pwm {
40 compatible = "nordic,nrf-sw-pwm";
|
| /Zephyr-Core-3.6.0/soc/riscv/nordic_nrf/common/vpr/ |
| D | soc_irq.S | 22 sw t0, __soc_esf_t_minttresh_OFFSET(a0)
|
| /Zephyr-Core-3.6.0/samples/boards/nrf/mesh/onoff-app/src/ |
| D | main.c | 268 static struct switch_data sw; variable
433 k_timer_start(&sw.button_timer, K_SECONDS(1), K_NO_WAIT); in button_pressed()
443 sw.sw_num = pin_to_sw(pin_pos); in button_pressed()
459 k_work_submit(&sw.button_work); in button_cnt_timer()
586 k_work_init(&sw.button_work, button_pressed_worker); in main()
589 k_timer_init(&sw.button_timer, button_cnt_timer, NULL); in main()
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| /Zephyr-Core-3.6.0/dts/arm/nordic/ |
| D | nrf54l_common.dtsi | 30 sw_pwm: sw-pwm {
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| /Zephyr-Core-3.6.0/arch/mips/core/ |
| D | reset.S | 41 sw t2, 0(t0)
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| /Zephyr-Core-3.6.0/include/zephyr/arch/mips/ |
| D | arch.h | 26 #define OP_STOREREG sw
|
| /Zephyr-Core-3.6.0/soc/riscv/neorv32/ |
| D | reset.S | 56 1: sw x0, 0(x8)
|
| /Zephyr-Core-3.6.0/tests/subsys/mem_mgmt/mem_attr_heap/boards/ |
| D | qemu_cortex_m3.overlay | 3 #include <zephyr/dt-bindings/memory-attr/memory-attr-sw.h>
|
| /Zephyr-Core-3.6.0/boards/posix/nrf_bsim/ |
| D | nrf5340bsim_nrf5340_cpunet.dts | 50 /delete-node/ sw-pwm;
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| D | nrf52_bsim.dts | 65 /delete-node/ sw-pwm;
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| D | nrf5340bsim_nrf5340_cpuapp.dts | 94 /delete-node/ sw-pwm;
|
| /Zephyr-Core-3.6.0/doc/services/pm/ |
| D | power_domain.rst | 46 domain:sw -> devA:sw [label="action_cb(PM_DEVICE_ACTION_TURN_ON)"]
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