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Searched refs:pulse_cycles (Results 1 – 25 of 37) sorted by relevance

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/Zephyr-Core-3.6.0/drivers/pwm/
Dpwm_nrf_sw.c74 uint32_t pulse_cycles[PWM_0_MAP_SIZE]; member
99 uint32_t pulse_cycles) in pwm_period_check() argument
104 if ((pulse_cycles == 0U) || (pulse_cycles == period_cycles)) { in pwm_period_check()
111 (data->pulse_cycles[i] != 0U) && in pwm_period_check()
121 uint32_t period_cycles, uint32_t pulse_cycles, in pwm_nrf_sw_set_cycles() argument
145 pulse_cycles); in pwm_nrf_sw_set_cycles()
172 channel, period_cycles, pulse_cycles); in pwm_nrf_sw_set_cycles()
186 if (pulse_cycles == 0 || pulse_cycles == period_cycles) { in pwm_nrf_sw_set_cycles()
188 pulse_cycles == 0 ? !active_level in pwm_nrf_sw_set_cycles()
195 data->pulse_cycles[channel] = 0U; in pwm_nrf_sw_set_cycles()
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Dpwm_xlnx_axi_timer.c67 uint32_t pulse_cycles, pwm_flags_t flags) in xlnx_axi_timer_set_cycles() argument
79 LOG_DBG("period = 0x%08x, pulse = 0x%08x", period_cycles, pulse_cycles); in xlnx_axi_timer_set_cycles()
81 if (pulse_cycles == 0) { in xlnx_axi_timer_set_cycles()
89 } else if (pulse_cycles == period_cycles) { in xlnx_axi_timer_set_cycles()
122 if ((period_cycles - pulse_cycles) < 2) { in xlnx_axi_timer_set_cycles()
128 tlr1 = period_cycles - pulse_cycles - 2; in xlnx_axi_timer_set_cycles()
130 if (pulse_cycles < 2) { in xlnx_axi_timer_set_cycles()
136 tlr1 = pulse_cycles - 2; in xlnx_axi_timer_set_cycles()
Dpwm_mchp_xec_bbled.c165 static uint32_t xec_pwmbb_compute_dc(uint32_t period_cycles, uint32_t pulse_cycles) in xec_pwmbb_compute_dc() argument
169 if (pulse_cycles >= period_cycles) { in xec_pwmbb_compute_dc()
177 dc = (256U * pulse_cycles) / period_cycles; in xec_pwmbb_compute_dc()
247 static int pwm_bbled_xec_check_cycles(uint32_t period_cycles, uint32_t pulse_cycles) in pwm_bbled_xec_check_cycles() argument
253 if ((pulse_cycles < 256U) || (pulse_cycles > (4096U * 256U))) { in pwm_bbled_xec_check_cycles()
261 uint32_t period_cycles, uint32_t pulse_cycles, in pwm_bbled_xec_set_cycles() argument
278 if ((pulse_cycles == 0U) && (period_cycles == 0U)) { /* Controller off, clocks gated */ in pwm_bbled_xec_set_cycles()
281 } else if ((pulse_cycles == 0U) && (period_cycles > 0U)) { in pwm_bbled_xec_set_cycles()
284 } else if ((pulse_cycles > 0U) && (period_cycles == 0U)) { in pwm_bbled_xec_set_cycles()
288 ret = pwm_bbled_xec_check_cycles(period_cycles, pulse_cycles); in pwm_bbled_xec_set_cycles()
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Dpwm_rcar.c90 uint32_t *period_cycles, uint32_t *pulse_cycles) in pwm_rcar_update_clk() argument
106 *pulse_cycles /= 2; in pwm_rcar_update_clk()
120 *pulse_cycles *= 2; in pwm_rcar_update_clk()
136 uint32_t pulse_cycles, pwm_flags_t flags) in pwm_rcar_set_cycles() argument
151 if (period_cycles == 0U || pulse_cycles == 0U || pulse_cycles > period_cycles) { in pwm_rcar_set_cycles()
157 config->reg_addr, pulse_cycles, period_cycles, in pwm_rcar_set_cycles()
158 (pulse_cycles * 100U / period_cycles)); in pwm_rcar_set_cycles()
176 ret = pwm_rcar_update_clk(config, channel, &period_cycles, &pulse_cycles); in pwm_rcar_set_cycles()
191 reg_val |= (pulse_cycles << RCAR_PWM_CNT_PH_SHIFT); in pwm_rcar_set_cycles()
Dpwm_mcux_ctimer.c128 uint32_t pulse_cycles, uint32_t period_channel, in mcux_ctimer_pwm_update_state() argument
136 data->channel_states[pulse_channel].cycles = pulse_cycles; in mcux_ctimer_pwm_update_state()
145 uint32_t period_cycles, uint32_t pulse_cycles, in mcux_ctimer_pwm_set_cycles() argument
172 if (pulse_cycles == 0) { in mcux_ctimer_pwm_set_cycles()
174 pulse_cycles = period_cycles + 1; in mcux_ctimer_pwm_set_cycles()
176 pulse_cycles = period_cycles - pulse_cycles; in mcux_ctimer_pwm_set_cycles()
181 pulse_cycles, false); in mcux_ctimer_pwm_set_cycles()
186 mcux_ctimer_pwm_update_state(data, pulse_channel, pulse_cycles, period_channel, in mcux_ctimer_pwm_set_cycles()
Dpwm_handlers.c53 uint32_t *pulse_cycles, in z_vrfy_pwm_capture_cycles() argument
71 if (pulse_cycles != NULL) { in z_vrfy_pwm_capture_cycles()
72 K_OOPS(k_usermode_to_copy(pulse_cycles, &pulse, in z_vrfy_pwm_capture_cycles()
73 sizeof(*pulse_cycles))); in z_vrfy_pwm_capture_cycles()
Dpwm_gd32.c61 uint32_t period_cycles, uint32_t pulse_cycles, in pwm_gd32_set_cycles() argument
91 TIMER_CH0CV(config->reg) = pulse_cycles; in pwm_gd32_set_cycles()
94 TIMER_CH1CV(config->reg) = pulse_cycles; in pwm_gd32_set_cycles()
97 TIMER_CH2CV(config->reg) = pulse_cycles; in pwm_gd32_set_cycles()
100 TIMER_CH3CV(config->reg) = pulse_cycles; in pwm_gd32_set_cycles()
Dpwm_nrfx.c119 uint32_t period_cycles, uint32_t pulse_cycles, in pwm_nrfx_set_cycles() argument
144 pulse_cycles /= 2; in pwm_nrfx_set_cycles()
147 if (pulse_cycles == 0) { in pwm_nrfx_set_cycles()
150 } else if (pulse_cycles >= period_cycles) { in pwm_nrfx_set_cycles()
163 compare_value = (uint16_t)(pulse_cycles >> data->prescaler); in pwm_nrfx_set_cycles()
170 channel, pulse_cycles, period_cycles, data->prescaler); in pwm_nrfx_set_cycles()
182 uint32_t out_level = (pulse_cycles == 0) ? 0 : 1; in pwm_nrfx_set_cycles()
Dpwm_imx.c50 uint32_t period_cycles, uint32_t pulse_cycles, in imx_pwm_set_cycles() argument
72 " duty_cycle=%d\n", enabled, pulse_cycles, period_cycles, in imx_pwm_set_cycles()
73 (pulse_cycles * 100U / period_cycles)); in imx_pwm_set_cycles()
119 PWM_PWMSAR_REG(config->base) = pulse_cycles; in imx_pwm_set_cycles()
Dpwm_xmc4xxx_ccu4.c52 uint32_t period_cycles, uint32_t pulse_cycles, in pwm_xmc4xxx_ccu4_set_cycles() argument
63 if (period_cycles == 0 || period_cycles > UINT16_MAX + 1 || pulse_cycles > UINT16_MAX) { in pwm_xmc4xxx_ccu4_set_cycles()
69 slice->CRS = period_cycles - pulse_cycles; in pwm_xmc4xxx_ccu4_set_cycles()
Dpwm_sam.c47 uint32_t period_cycles, uint32_t pulse_cycles, in sam_pwm_set_cycles() argument
80 pwm->PWM_CH_NUM[channel].PWM_CDTY = pulse_cycles; in sam_pwm_set_cycles()
86 pwm->PWM_CH_NUM[channel].PWM_CDTYUPD = pulse_cycles; in sam_pwm_set_cycles()
Dpwm_b91.c59 uint32_t period_cycles, uint32_t pulse_cycles, in pwm_b91_set_cycles() argument
71 (pulse_cycles > 0xFFFFu)) { in pwm_b91_set_cycles()
83 pwm_set_tcmp(channel, pulse_cycles); in pwm_b91_set_cycles()
Dpwm_sam0_tcc.c60 uint32_t period_cycles, uint32_t pulse_cycles, in pwm_sam0_set_cycles() argument
73 if (period_cycles >= top || pulse_cycles >= top) { in pwm_sam0_set_cycles()
83 regs->CCBUF[channel].reg = TCC_CCBUF_CCBUF(pulse_cycles); in pwm_sam0_set_cycles()
87 regs->CCB[channel].reg = TCC_CCB_CCB(pulse_cycles); in pwm_sam0_set_cycles()
Dpwm_xmc4xxx_ccu8.c88 uint32_t period_cycles, uint32_t pulse_cycles, in pwm_xmc4xxx_ccu8_set_cycles() argument
101 if (period_cycles == 0 || period_cycles > UINT16_MAX + 1 || pulse_cycles > UINT16_MAX) { in pwm_xmc4xxx_ccu8_set_cycles()
109 slice->CR2S = period_cycles - pulse_cycles; in pwm_xmc4xxx_ccu8_set_cycles()
111 slice->CR1S = period_cycles - pulse_cycles; in pwm_xmc4xxx_ccu8_set_cycles()
Dpwm_litex.c37 uint32_t pulse_cycles, pwm_flags_t flags) in pwm_litex_set_cycles() argument
46 litex_write32(pulse_cycles, cfg->reg_width); in pwm_litex_set_cycles()
Dpwm_mcux.c41 uint32_t period_cycles, uint32_t pulse_cycles, in mcux_pwm_set_cycles() argument
119 (uint16_t)pulse_cycles); in mcux_pwm_set_cycles()
132 (uint16_t)pulse_cycles); in mcux_pwm_set_cycles()
146 (uint16_t)pulse_cycles); in mcux_pwm_set_cycles()
153 (uint16_t)pulse_cycles); in mcux_pwm_set_cycles()
Dpwm_capture.c24 uint32_t pulse_cycles, int status, in z_pwm_capture_cycles_callback() argument
30 data->pulse = pulse_cycles; in z_pwm_capture_cycles_callback()
Dpwm_mchp_xec.c318 uint32_t period_cycles, uint32_t pulse_cycles, in pwm_xec_set_cycles() argument
333 on = pulse_cycles; in pwm_xec_set_cycles()
334 off = period_cycles - pulse_cycles; in pwm_xec_set_cycles()
342 if ((pulse_cycles == 0U) && (period_cycles == 0U)) { in pwm_xec_set_cycles()
344 } else if ((pulse_cycles == 0U) && (period_cycles > 0U)) { in pwm_xec_set_cycles()
347 } else if ((pulse_cycles > 0U) && (period_cycles == 0U)) { in pwm_xec_set_cycles()
Dpwm_rpi_pico.c105 uint32_t pulse_cycles, pwm_flags_t flags) in pwm_rpi_set_cycles() argument
112 pulse_cycles > PWM_RPI_PICO_COUNTER_TOP_MAX) { in pwm_rpi_set_cycles()
124 pwm_set_chan_level(slice, pico_channel, pulse_cycles); in pwm_rpi_set_cycles()
Dpwm_sifive.c110 uint32_t period_cycles, uint32_t pulse_cycles, in pwm_sifive_set_cycles() argument
170 sys_write32((pulse_cycles >> pwmscale), in pwm_sifive_set_cycles()
178 (pulse_cycles >> pwmscale)); in pwm_sifive_set_cycles()
Dpwm_npcx.c81 uint32_t period_cycles, uint32_t pulse_cycles, in pwm_npcx_set_cycles() argument
105 if (pulse_cycles == 0) { in pwm_npcx_set_cycles()
128 dcr = (pulse_cycles / prescaler) - 1; in pwm_npcx_set_cycles()
Dpwm_ite_it8xxx2.c91 uint32_t pulse_cycles, pwm_flags_t flags) in pwm_it8xxx2_set_cycles() argument
115 if (pulse_cycles == 0) { in pwm_it8xxx2_set_cycles()
202 *reg_dcr = (ctr * pulse_cycles) / period_cycles; in pwm_it8xxx2_set_cycles()
Dpwm_mcux_tpm.c45 uint32_t period_cycles, uint32_t pulse_cycles, in mcux_tpm_set_cycles() argument
62 duty_cycle = pulse_cycles * 100U / period_cycles; in mcux_tpm_set_cycles()
72 pulse_cycles, period_cycles, duty_cycle, flags); in mcux_tpm_set_cycles()
Dpwm_rv32m1_tpm.c44 uint32_t period_cycles, uint32_t pulse_cycles, in rv32m1_tpm_set_cycles() argument
61 duty_cycle = pulse_cycles * 100U / period_cycles; in rv32m1_tpm_set_cycles()
71 pulse_cycles, period_cycles, duty_cycle, flags); in rv32m1_tpm_set_cycles()
/Zephyr-Core-3.6.0/include/zephyr/drivers/
Dpwm.h392 uint32_t pulse_cycles,
401 uint32_t period_cycles, uint32_t pulse_cycles,
539 uint64_t pulse_cycles; in pwm_set() local
553 pulse_cycles = (pulse * cycles_per_sec) / NSEC_PER_SEC; in pwm_set()
554 if (pulse_cycles > UINT32_MAX) { in pwm_set()
559 (uint32_t)pulse_cycles, flags); in pwm_set()
851 uint32_t pulse_cycles; in pwm_capture_usec() local
855 &pulse_cycles, timeout); in pwm_capture_usec()
865 err = pwm_cycles_to_usec(dev, channel, pulse_cycles, pulse); in pwm_capture_usec()
906 uint32_t pulse_cycles; in pwm_capture_nsec() local
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