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Searched refs:pincfg (Results 1 – 25 of 145) sorted by relevance

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/Zephyr-latest/soc/nordic/common/
Dpinctrl_soc.h104 #define NRF_GET_FUN(pincfg) (((pincfg) >> NRF_FUN_POS) & NRF_FUN_MSK) argument
111 #define NRF_GET_CLOCKPIN_ENABLE(pincfg) \ argument
112 (((pincfg) >> NRF_CLOCKPIN_ENABLE_POS) & NRF_CLOCKPIN_ENABLE_MSK)
119 #define NRF_GET_GPD_FAST_ACTIVE1(pincfg) \ argument
120 (((pincfg) >> NRF_GPD_FAST_ACTIVE1_POS) & NRF_GPD_FAST_ACTIVE1_MSK)
127 #define NRF_GET_INVERT(pincfg) (((pincfg) >> NRF_INVERT_POS) & NRF_INVERT_MSK) argument
134 #define NRF_GET_LP(pincfg) (((pincfg) >> NRF_LP_POS) & NRF_LP_MSK) argument
141 #define NRF_GET_DRIVE(pincfg) (((pincfg) >> NRF_DRIVE_POS) & NRF_DRIVE_MSK) argument
148 #define NRF_GET_PULL(pincfg) (((pincfg) >> NRF_PULL_POS) & NRF_PULL_MSK) argument
155 #define NRF_GET_PIN(pincfg) (((pincfg) >> NRF_PIN_POS) & NRF_PIN_MSK) argument
/Zephyr-latest/drivers/gpio/
Dgpio_ambiq.c44 am_hal_gpio_pincfg_t pincfg = g_AM_HAL_GPIO_DEFAULT; in ambiq_gpio_pin_configure() local
47 pincfg = g_AM_HAL_GPIO_INPUT; in ambiq_gpio_pin_configure()
49 pincfg.ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K; in ambiq_gpio_pin_configure()
51 pincfg.ePullup = AM_HAL_GPIO_PIN_PULLDOWN; in ambiq_gpio_pin_configure()
57 pincfg.eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN; in ambiq_gpio_pin_configure()
59 pincfg.ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K; in ambiq_gpio_pin_configure()
61 pincfg.ePullup = AM_HAL_GPIO_PIN_PULLDOWN; in ambiq_gpio_pin_configure()
65 pincfg.eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL; in ambiq_gpio_pin_configure()
69 pincfg = g_AM_HAL_GPIO_DEFAULT; in ambiq_gpio_pin_configure()
73 pincfg.eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVEHIGH; in ambiq_gpio_pin_configure()
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Dgpio_renesas_ra.c147 struct ra_pinctrl_soc_pin pincfg = {0}; in gpio_ra_pin_configure() local
158 pincfg.cfg |= BIT(R_PFS_PORT_PIN_PmnPFS_PDR_Pos); in gpio_ra_pin_configure()
162 pincfg.cfg |= BIT(R_PFS_PORT_PIN_PmnPFS_PCR_Pos); in gpio_ra_pin_configure()
166 pincfg.cfg |= BIT(R_PFS_PORT_PIN_PmnPFS_NCODR_Pos); in gpio_ra_pin_configure()
170 pincfg.cfg |= BIT(R_PFS_PORT_PIN_PmnPFS_ISEL_Pos); in gpio_ra_pin_configure()
173 pincfg.cfg &= ~BIT(R_PFS_PORT_PIN_PmnPFS_PMR_Pos); in gpio_ra_pin_configure()
175 pincfg.pin_num = pin; in gpio_ra_pin_configure()
176 pincfg.port_num = config->port; in gpio_ra_pin_configure()
225 return pinctrl_configure_pins(&pincfg, 1, PINCTRL_REG_NONE); in gpio_ra_pin_configure()
233 struct ra_pinctrl_soc_pin pincfg; in gpio_ra_pin_get_config() local
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Dgpio_sam0.c57 PORT_PINCFG_Type pincfg = { in gpio_sam0_config() local
67 pincfg.bit.INEN = 1; in gpio_sam0_config()
87 pincfg.bit.PULLEN = 1; in gpio_sam0_config()
99 && (pincfg.bit.INEN != 0)); in gpio_sam0_config()
102 regs->PINCFG[pin] = pincfg; in gpio_sam0_config()
169 PORT_PINCFG_Type pincfg = { in gpio_sam0_pin_interrupt_configure() local
179 pincfg.bit.PMUXEN = 0; in gpio_sam0_pin_interrupt_configure()
198 if ((pincfg.bit.INEN == 0) in gpio_sam0_pin_interrupt_configure()
205 pincfg.bit.PMUXEN = 1; in gpio_sam0_pin_interrupt_configure()
248 regs->PINCFG[pin] = pincfg; in gpio_sam0_pin_interrupt_configure()
Dgpio_stm32.c52 static int gpio_stm32_flags_to_conf(gpio_flags_t flags, uint32_t *pincfg) in gpio_stm32_flags_to_conf() argument
58 *pincfg = STM32_PINCFG_MODE_OUTPUT; in gpio_stm32_flags_to_conf()
62 *pincfg |= STM32_PINCFG_OPEN_DRAIN; in gpio_stm32_flags_to_conf()
68 *pincfg |= STM32_PINCFG_PUSH_PULL; in gpio_stm32_flags_to_conf()
72 *pincfg |= STM32_PINCFG_PULL_UP; in gpio_stm32_flags_to_conf()
74 *pincfg |= STM32_PINCFG_PULL_DOWN; in gpio_stm32_flags_to_conf()
80 *pincfg = STM32_PINCFG_MODE_INPUT; in gpio_stm32_flags_to_conf()
83 *pincfg |= STM32_PINCFG_PULL_UP; in gpio_stm32_flags_to_conf()
85 *pincfg |= STM32_PINCFG_PULL_DOWN; in gpio_stm32_flags_to_conf()
87 *pincfg |= STM32_PINCFG_FLOATING; in gpio_stm32_flags_to_conf()
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/Zephyr-latest/drivers/pinctrl/
Dpinctrl_max32.c31 int pincfg; in pinctrl_configure_pin() local
37 pincfg = soc_pin.pincfg; in pinctrl_configure_pin()
46 if (pincfg & BIT(MAX32_BIAS_PULL_UP_SHIFT)) { in pinctrl_configure_pin()
48 } else if (pincfg & BIT(MAX32_BIAS_PULL_DOWN_SHIFT)) { in pinctrl_configure_pin()
54 if (pincfg & BIT(MAX32_INPUT_ENABLE_SHIFT)) { in pinctrl_configure_pin()
56 } else if (pincfg & BIT(MAX32_OUTPUT_ENABLE_SHIFT)) { in pinctrl_configure_pin()
63 if (pincfg & BIT(MAX32_POWER_SOURCE_SHIFT)) { in pinctrl_configure_pin()
69 gpio_cfg.drvstr = (pincfg >> MAX32_DRV_STRENGTH_SHIFT) & MAX32_DRV_STRENGTH_MASK; in pinctrl_configure_pin()
75 if (pincfg & BIT(MAX32_OUTPUT_ENABLE_SHIFT)) { in pinctrl_configure_pin()
76 if (pincfg & BIT(MAX32_OUTPUT_HIGH_SHIFT)) { in pinctrl_configure_pin()
Dpinctrl_ti_cc32xx.c24 static int pinctrl_configure_pin(pinctrl_soc_pin_t pincfg) in pinctrl_configure_pin() argument
28 pin = (pincfg >> TI_CC32XX_PIN_POS) & TI_CC32XX_PIN_MSK; in pinctrl_configure_pin()
33 sys_write32(pincfg & MEM_GPIO_PAD_CONFIG_MSK, DT_INST_REG_ADDR(0) + (pin2pad[pin] << 2U)); in pinctrl_configure_pin()
Dpinctrl_ite_it8xxx2.c76 uint32_t pincfg = pins->pincfg; in pinctrl_it8xxx2_set() local
83 switch (IT8XXX2_DT_PINCFG_PUPDR(pincfg)) { in pinctrl_it8xxx2_set()
108 switch (IT8XXX2_DT_PINCFG_VOLTAGE(pincfg)) { in pinctrl_it8xxx2_set()
114 __ASSERT(!(IT8XXX2_DT_PINCFG_PUPDR(pincfg) in pinctrl_it8xxx2_set()
127 if (IT8XXX2_DT_PINCFG_IMPEDANCE(pincfg)) { in pinctrl_it8xxx2_set()
134 IT8XXX2_DT_PINCFG_DRIVE_CURRENT(pincfg) != IT8XXX2_DRIVE_DEFAULT) { in pinctrl_it8xxx2_set()
135 if (IT8XXX2_DT_PINCFG_DRIVE_CURRENT(pincfg) & IT8XXX2_PDSCX_MASK) { in pinctrl_it8xxx2_set()
174 if (IT8XXX2_DT_PINCFG_INPUT(pins->pincfg)) { in pinctrl_gpio_it8xxx2_configure_pins()
239 uint32_t pincfg = pins->pincfg; in pinctrl_kscan_it8xxx2_set() local
247 switch (IT8XXX2_DT_PINCFG_PULLUP(pincfg)) { in pinctrl_kscan_it8xxx2_set()
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Dpinctrl_stm32.c246 pin_cgf = pins[i].pincfg | STM32_MODE_OUTPUT | STM32_CNF_ALT_FUNC; in pinctrl_configure_pins()
248 pin_cgf = pins[i].pincfg | STM32_MODE_INPUT | STM32_CNF_IN_ANALOG; in pinctrl_configure_pins()
250 pin_cgf = pins[i].pincfg | STM32_MODE_INPUT; in pinctrl_configure_pins()
258 pin_cgf = pins[i].pincfg | STM32_MODE_OUTPUT | STM32_CNF_GP_OUTPUT; in pinctrl_configure_pins()
265 pin_cgf = pins[i].pincfg | STM32_MODER_ALT_MODE; in pinctrl_configure_pins()
269 pin_cgf = pins[i].pincfg; in pinctrl_configure_pins()
/Zephyr-latest/soc/silabs/common/
Dpinctrl_soc.h116 #define GECKO_GET_FUN(pincfg) (((pincfg) >> GECKO_FUN_POS) & GECKO_FUN_MSK)
123 #define GECKO_GET_PORT(pincfg) (((pincfg) >> GECKO_PORT_POS) & GECKO_PORT_MSK)
130 #define GECKO_GET_PIN(pincfg) (((pincfg) >> GECKO_PIN_POS) & GECKO_PIN_MSK)
137 #define GECKO_GET_LOC(pincfg) (((pincfg) >> GECKO_LOC_POS) & GECKO_LOC_MSK)
144 #define GECKO_GET_SPEED(pincfg) (((pincfg) >> GECKO_SPEED_POS) & GECKO_SPEED_MSK)
/Zephyr-latest/soc/gd/gd32/common/
Dpinctrl_soc.h171 #define GD32_PUPD_GET(pincfg) \ argument
172 (((pincfg) >> GD32_PUPD_POS) & GD32_PUPD_MSK)
179 #define GD32_OTYPE_GET(pincfg) \ argument
180 (((pincfg) >> GD32_OTYPE_POS) & GD32_OTYPE_MSK)
187 #define GD32_OSPEED_GET(pincfg) \ argument
188 (((pincfg) >> GD32_OSPEED_POS) & GD32_OSPEED_MSK)
/Zephyr-latest/soc/atmel/sam0/common/
Dsoc_port.c40 PORT_PINCFG_Type pincfg = { .reg = 0 }; in soc_port_configure() local
43 pg->PINCFG[pin->pinum] = pincfg; in soc_port_configure()
57 pincfg.bit.PULLEN = 1; in soc_port_configure()
61 pincfg.bit.INEN = 1; in soc_port_configure()
69 pincfg.bit.DRVSTR = 1; in soc_port_configure()
72 pg->PINCFG[pin->pinum] = pincfg; in soc_port_configure()
/Zephyr-latest/tests/drivers/pinctrl/api/src/
Dpinctrl_soc.h57 #define TEST_GET_PULL(pincfg) (((pincfg) >> TEST_PULL_POS) & TEST_PULL_MSK) argument
64 #define TEST_GET_PIN(pincfg) (((pincfg) >> TEST_PIN_POS) & TEST_PIN_MSK) argument
/Zephyr-latest/drivers/pinctrl/renesas/ra/
Dpinctrl_ra.c30 int ra_pinctrl_query_config(uint32_t port, uint32_t pin, pinctrl_soc_pin_t *pincfg) in ra_pinctrl_query_config() argument
36 pincfg->port_num = port; in ra_pinctrl_query_config()
37 pincfg->pin_num = pin; in ra_pinctrl_query_config()
39 pincfg->cfg = R_PFS->PORT[port].PIN[pin].PmnPFS; in ra_pinctrl_query_config()
/Zephyr-latest/drivers/memc/
Dmemc_renesas_ra_sdram.c16 const struct pinctrl_dev_config *pincfg; member
24 err = pinctrl_apply_state(config->pincfg, PINCTRL_STATE_DEFAULT); in renesas_ra_sdram_init()
37 .pincfg = PINCTRL_DT_INST_DEV_CONFIG_GET(0),
/Zephyr-latest/include/zephyr/drivers/pinctrl/
Dpinctrl_soc_sam_common.h105 #define SAM_PINCTRL_FLAG_GET(pincfg, pos) \ argument
106 (((pincfg) >> pos) & SAM_PINCTRL_FLAG_MASK)
108 #define SAM_PINCTRL_FLAGS_GET(pincfg) \ argument
109 (((pincfg) >> SAM_PINCTRL_FLAGS_POS) & SAM_PINCTRL_FLAGS_MASK)
/Zephyr-latest/drivers/ethernet/eth_nxp_enet_qos/
Deth_nxp_enet_qos.c27 return pinctrl_apply_state(config->pincfg, PINCTRL_STATE_DEFAULT); in nxp_enet_qos_init()
34 .pincfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \
/Zephyr-latest/soc/adi/max32/common/
Dpinctrl_soc.h21 uint32_t pincfg; member
37 .pincfg = Z_PINCTRL_MAX32_PINCFG_INIT(DT_PROP_BY_IDX(node_id, state_prop, idx))},
/Zephyr-latest/drivers/mdio/
Dmdio_nxp_s32_netc.c18 const struct pinctrl_dev_config *pincfg; member
60 err = pinctrl_apply_state(cfg->pincfg, PINCTRL_STATE_DEFAULT); in nxp_s32_mdio_initialize()
85 .pincfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \
Dmdio_stm32_hal.c30 const struct pinctrl_dev_config *pincfg; member
92 ret = pinctrl_apply_state(config->pincfg, PINCTRL_STATE_DEFAULT); in mdio_stm32_init()
116 .pincfg = PINCTRL_DT_INST_DEV_CONFIG_GET(inst), \
Dmdio_nxp_imx_netc.c19 const struct pinctrl_dev_config *pincfg; member
63 err = pinctrl_apply_state(cfg->pincfg, PINCTRL_STATE_DEFAULT); in nxp_imx_netc_mdio_initialize()
92 .pincfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \
Dmdio_renesas_ra.c24 const struct pinctrl_dev_config *pincfg; member
86 err = pinctrl_apply_state(cfg->pincfg, PINCTRL_STATE_DEFAULT); in renesas_ra_mdio_initialize()
118 .pincfg = PINCTRL_DT_INST_DEV_CONFIG_GET(node)}; \
/Zephyr-latest/drivers/dac/
Ddac_mcux_dac32.c23 const struct pinctrl_dev_config *pincfg; member
101 return pinctrl_apply_state(config->pincfg, PINCTRL_STATE_DEFAULT); in mcux_dac32_init()
123 .pincfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \
/Zephyr-latest/soc/espressif/esp32/
Dpinctrl_soc.h27 uint32_t pincfg; member
62 .pincfg = Z_PINCTRL_ESP32_PINCFG_INIT(node_id)},
/Zephyr-latest/soc/espressif/esp32c2/
Dpinctrl_soc.h27 uint32_t pincfg; member
62 .pincfg = Z_PINCTRL_ESP32_PINCFG_INIT(node_id)},

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