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Searched refs:TG1_T1_LEVEL_INTR_SOURCE (Results 1 – 6 of 6) sorted by relevance

/Zephyr-Core-3.6.0/include/zephyr/dt-bindings/interrupt-controller/
Desp-xtensa-intmux.h29 #define TG1_T1_LEVEL_INTR_SOURCE 19 /* TIMER_GROUP1, TIMER1, level */ macro
Desp32s2-xtensa-intmux.h30 #define TG1_T1_LEVEL_INTR_SOURCE 20 /* TIMER_GROUP1, TIMER1, level */ macro
Desp32s3-xtensa-intmux.h60 #define TG1_T1_LEVEL_INTR_SOURCE 54 /* interrupt of TIMER_GROUP1, TIMER1, EDGE*/ macro
/Zephyr-Core-3.6.0/dts/xtensa/espressif/esp32s2/
Desp32s2_common.dtsi252 interrupts = <TG1_T1_LEVEL_INTR_SOURCE>;
/Zephyr-Core-3.6.0/dts/xtensa/espressif/esp32s3/
Desp32s3_common.dtsi332 interrupts = <TG1_T1_LEVEL_INTR_SOURCE>;
/Zephyr-Core-3.6.0/dts/xtensa/espressif/esp32/
Desp32_common.dtsi396 interrupts = <TG1_T1_LEVEL_INTR_SOURCE>;