TG0_WDT_LEVEL_INTR_SOURCE (reference) in projects: Zephyr-Core-3.6.0

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Searched refs:TG0_WDT_LEVEL_INTR_SOURCE (Results 1 – 8 of 8) sorted by relevance

/Zephyr-Core-3.6.0/include/zephyr/dt-bindings/interrupt-controller/
D	esp-esp32c3-intmux.h	`43 #define TG0_WDT_LEVEL_INTR_SOURCE 33 macro`
D	esp-xtensa-intmux.h	`26 #define TG0_WDT_LEVEL_INTR_SOURCE 16 /* TIMER_GROUP0, WATCHDOG, level */ macro`
D	esp32s2-xtensa-intmux.h	`27 #define TG0_WDT_LEVEL_INTR_SOURCE 17 /* TIMER_GROUP0, WATCHDOG, level */ macro`
D	esp32s3-xtensa-intmux.h	`58 #define TG0_WDT_LEVEL_INTR_SOURCE 52 /* interrupt of TIMER_GROUP0, WATCH DOG, EDGE*/ macro`
/Zephyr-Core-3.6.0/dts/riscv/espressif/esp32c3/
D	esp32c3_common.dtsi	`239 interrupts = <TG0_WDT_LEVEL_INTR_SOURCE>;`
/Zephyr-Core-3.6.0/dts/xtensa/espressif/esp32s2/
D	esp32s2_common.dtsi	`287 interrupts = <TG0_WDT_LEVEL_INTR_SOURCE>;`
/Zephyr-Core-3.6.0/dts/xtensa/espressif/esp32s3/
D	esp32s3_common.dtsi	`339 interrupts = <TG0_WDT_LEVEL_INTR_SOURCE>;`
/Zephyr-Core-3.6.0/dts/xtensa/espressif/esp32/
D	esp32_common.dtsi	`314 interrupts = <TG0_WDT_LEVEL_INTR_SOURCE>;`

TraceRecorderSource-2.7.6
TraceRecorderSource-3.4.0
Zephyr-Core-2.7.6
Zephyr-Core-3.4.0
Zephyr-Core-3.5.0
Zephyr-Core-3.6.0
Zephyr-Core-3.7.0
acpica-3.5.0
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babblesim_ext_2G4_channel_multiatt-3.4.0
babblesim_ext_2G4_channel_multiatt-3.7.0-3.6.0-3.5.0
babblesim_ext_2G4_device_WLAN_actmod-3.7.0-3.6.0-3.5.0-3.4.0
babblesim_ext_2G4_device_burst_interferer-3.7.0-3.6.0-3.5.0-3.4.0
babblesim_ext_2G4_device_playback-3.6.0-3.5.0-3.4.0
babblesim_ext_2G4_device_playback-3.7.0
babblesim_ext_2G4_libPhyComv1-3.6.0-3.5.0-3.4.0
babblesim_ext_2G4_libPhyComv1-3.7.0
babblesim_ext_2G4_modem_BLE_simple-3.4.0
babblesim_ext_2G4_modem_BLE_simple-3.6.0-3.5.0
babblesim_ext_2G4_modem_BLE_simple-3.7.0
babblesim_ext_2G4_modem_magic-3.6.0-3.5.0-3.4.0
babblesim_ext_2G4_modem_magic-3.7.0
babblesim_ext_2G4_phy_v1-3.4.0
babblesim_ext_2G4_phy_v1-3.6.0-3.5.0
babblesim_ext_2G4_phy_v1-3.7.0
babblesim_ext_libCryptov1-3.7.0-3.6.0-3.5.0-3.4.0
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