Home
last modified time | relevance | path

Searched refs:TG0_T1_LEVEL_INTR_SOURCE (Results 1 – 6 of 6) sorted by relevance

/Zephyr-Core-3.6.0/include/zephyr/dt-bindings/interrupt-controller/
Desp-xtensa-intmux.h25 #define TG0_T1_LEVEL_INTR_SOURCE 15 /* TIMER_GROUP0, TIMER1, level */ macro
Desp32s2-xtensa-intmux.h26 #define TG0_T1_LEVEL_INTR_SOURCE 16 /* TIMER_GROUP0, TIMER1, level */ macro
Desp32s3-xtensa-intmux.h57 #define TG0_T1_LEVEL_INTR_SOURCE 51 /* interrupt of TIMER_GROUP0, TIMER1, EDGE*/ macro
/Zephyr-Core-3.6.0/dts/xtensa/espressif/esp32s2/
Desp32s2_common.dtsi232 interrupts = <TG0_T1_LEVEL_INTR_SOURCE>;
/Zephyr-Core-3.6.0/dts/xtensa/espressif/esp32s3/
Desp32s3_common.dtsi312 interrupts = <TG0_T1_LEVEL_INTR_SOURCE>;
/Zephyr-Core-3.6.0/dts/xtensa/espressif/esp32/
Desp32_common.dtsi376 interrupts = <TG0_T1_LEVEL_INTR_SOURCE>;