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Searched refs:SDRAM1_BASE (Results 1 – 6 of 6) sorted by relevance

/Zephyr-Core-3.6.0/soc/xtensa/nxp_adsp/imx8/include/
Dmemory.h18 #define SDRAM1_BASE 0x92C00000 macro
88 #define SDRAM1_BASE 0x92C00000 macro
134 #define SRAM_OUTBOX_BASE SDRAM1_BASE
/Zephyr-Core-3.6.0/soc/xtensa/nxp_adsp/imx8ulp/include/
Dmemory.h17 #define SDRAM1_BASE 0x1a800000 macro
84 #define SDRAM1_BASE 0x1a800000 macro
131 #define SRAM_OUTBOX_BASE SDRAM1_BASE
/Zephyr-Core-3.6.0/soc/xtensa/nxp_adsp/imx8m/include/
Dmemory.h23 #define SDRAM1_BASE 0x92C00000 macro
93 #define SDRAM1_BASE 0x92C00000 macro
141 #define SRAM_OUTBOX_BASE SDRAM1_BASE
/Zephyr-Core-3.6.0/soc/xtensa/nxp_adsp/imx8/
Dlinker.ld90 org = SDRAM1_BASE + SOF_MAILBOX_SIZE,
445 __stack = SDRAM1_BASE + SDRAM1_SIZE;
/Zephyr-Core-3.6.0/soc/xtensa/nxp_adsp/imx8m/
Dlinker.ld90 org = SDRAM1_BASE + SOF_MAILBOX_SIZE,
458 __stack = SDRAM1_BASE + SDRAM1_SIZE;
/Zephyr-Core-3.6.0/soc/xtensa/nxp_adsp/imx8ulp/
Dlinker.ld90 org = SDRAM1_BASE + SOF_MAILBOX_SIZE,
445 __stack = SDRAM1_BASE + SDRAM1_SIZE;