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Searched refs:DT_INST_CHILD (Results 1 – 25 of 34) sorted by relevance

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/Zephyr-latest/include/zephyr/devicetree/
Dport-endpoint.h37 COND_CODE_1(DT_NODE_EXISTS(DT_INST_CHILD(inst, ports)), \
38 (DT_CHILD(DT_INST_CHILD(inst, ports), port_##pid)), (DT_INST_CHILD(inst, port_##pid)))
89 (_DT_INST_PORT_BY_ID(inst, pid)), (DT_INST_CHILD(inst, port)))
/Zephyr-latest/drivers/display/
Ddisplay_stm32_ltdc.c556 .HSPolarity = (DT_PROP(DT_INST_CHILD(inst, display_timings), \
559 .VSPolarity = (DT_PROP(DT_INST_CHILD(inst, \
562 .DEPolarity = (DT_PROP(DT_INST_CHILD(inst, \
565 .PCPolarity = (DT_PROP(DT_INST_CHILD(inst, \
568 .HorizontalSync = DT_PROP(DT_INST_CHILD(inst, \
570 .VerticalSync = DT_PROP(DT_INST_CHILD(inst, \
572 .AccumulatedHBP = DT_PROP(DT_INST_CHILD(inst, \
574 DT_PROP(DT_INST_CHILD(inst, \
576 .AccumulatedVBP = DT_PROP(DT_INST_CHILD(inst, \
578 DT_PROP(DT_INST_CHILD(inst, \
[all …]
Ddisplay_mcux_dcnano_lcdif.c308 .hsw = DT_PROP(DT_INST_CHILD(n, display_timings), \
310 .hfp = DT_PROP(DT_INST_CHILD(n, display_timings), \
312 .hbp = DT_PROP(DT_INST_CHILD(n, display_timings), \
314 .vsw = DT_PROP(DT_INST_CHILD(n, display_timings), \
316 .vfp = DT_PROP(DT_INST_CHILD(n, display_timings), \
318 .vbp = DT_PROP(DT_INST_CHILD(n, display_timings), \
320 .polarityFlags = (DT_PROP(DT_INST_CHILD(n, \
324 (DT_PROP(DT_INST_CHILD(n, \
328 (DT_PROP(DT_INST_CHILD(n, \
332 (DT_PROP(DT_INST_CHILD(n, \
Ddisplay_renesas_ra.c356 DT_PROP(DT_INST_CHILD(id, display_timings), \
358 DT_PROP(DT_INST_CHILD(id, display_timings), \
360 DT_PROP(DT_INST_CHILD(id, display_timings), \
364 DT_PROP(DT_INST_CHILD(id, display_timings), \
367 DT_PROP(DT_INST_CHILD(id, display_timings), \
370 DT_PROP(DT_INST_CHILD(id, display_timings), \
374 DT_PROP(DT_INST_CHILD(id, display_timings), \
376 DT_PROP(DT_INST_CHILD(id, display_timings), \
378 DT_PROP(DT_INST_CHILD(id, display_timings), \
382 DT_PROP(DT_INST_CHILD(id, display_timings), \
[all …]
Ddisplay_renesas_lcdc.c36 !!(32000000U % DT_PROP(DT_INST_CHILD(0, display_timings), clock_frequency))
141 LCDC_SMARTBOND_CLK_DIV(DT_PROP(DT_INST_CHILD(0, display_timings), clock_frequency)); in display_smartbond_configure()
638 DT_PROP(DT_INST_CHILD(inst, display_timings), vsync_len), \
640 DT_PROP(DT_INST_CHILD(inst, display_timings), hsync_len), \
642 DT_PROP(DT_INST_CHILD(inst, display_timings), hfront_porch), \
644 DT_PROP(DT_INST_CHILD(inst, display_timings), vfront_porch), \
646 DT_PROP(DT_INST_CHILD(inst, display_timings), hback_porch), \
648 DT_PROP(DT_INST_CHILD(inst, display_timings), vback_porch), \
655 DT_PROP(DT_INST_CHILD(inst, display_timings), vsync_active) ? 0 : 1, \
657 DT_PROP(DT_INST_CHILD(inst, display_timings), vsync_active) ? 0 : 1, \
[all …]
Ddisplay_mcux_elcdif.c376 .hsw = DT_PROP(DT_INST_CHILD(id, display_timings), hsync_len), \
377 .hfp = DT_PROP(DT_INST_CHILD(id, display_timings), hfront_porch), \
378 .hbp = DT_PROP(DT_INST_CHILD(id, display_timings), hback_porch), \
379 .vsw = DT_PROP(DT_INST_CHILD(id, display_timings), vsync_len), \
380 .vfp = DT_PROP(DT_INST_CHILD(id, display_timings), vfront_porch), \
381 .vbp = DT_PROP(DT_INST_CHILD(id, display_timings), vback_porch), \
383 (DT_PROP(DT_INST_CHILD(id, display_timings), hsync_active) \
386 (DT_PROP(DT_INST_CHILD(id, display_timings), vsync_active) \
389 (DT_PROP(DT_INST_CHILD(id, display_timings), de_active) \
392 (DT_PROP(DT_INST_CHILD(id, display_timings), \
/Zephyr-latest/drivers/mipi_dsi/
Ddsi_renesas_ra.c229 .t_init = CLAMP(DT_PROP(DT_INST_CHILD(n, phys_timing), t_init), 0, 0x7FFF), \
230 .t_clk_prep = CLAMP(DT_PROP(DT_INST_CHILD(n, phys_timing), t_clk_prep), 0, 0xFF), \
231 .t_hs_prep = CLAMP(DT_PROP(DT_INST_CHILD(n, phys_timing), t_hs_prep), 0, 0xFF), \
232 .t_lp_exit = CLAMP(DT_PROP(DT_INST_CHILD(n, phys_timing), t_lp_exit), 0, 0xFF), \
235 .t_clk_zero = DT_PROP_BY_IDX(DT_INST_CHILD(n, phys_timing), \
237 .t_clk_pre = DT_PROP_BY_IDX(DT_INST_CHILD(n, phys_timing), \
239 .t_clk_post = DT_PROP_BY_IDX(DT_INST_CHILD(n, phys_timing), \
241 .t_clk_trail = DT_PROP_BY_IDX(DT_INST_CHILD(n, phys_timing), \
246 .t_hs_zero = DT_PROP_BY_IDX(DT_INST_CHILD(n, phys_timing), \
248 .t_hs_trail = DT_PROP_BY_IDX(DT_INST_CHILD(n, phys_timing), \
[all …]
/Zephyr-latest/drivers/regulator/
Dregulator_mpm54304.c86 DT_NODE_EXISTS(DT_INST_CHILD(inst, child)), \
87 (REGULATOR_MPM54304_DEFINE(DT_INST_CHILD(inst, child), child##inst, child_name)))
Dregulator_npm1100.c122 COND_CODE_1(DT_NODE_EXISTS(DT_INST_CHILD(inst, buck)), \
123 (REGULATOR_NPM1100_DEFINE_BUCK(DT_INST_CHILD(inst, buck), \
Dregulator_adp5360.c300 COND_CODE_1(DT_NODE_EXISTS(DT_INST_CHILD(inst, child)), \
301 (REGULATOR_ADP5360_DEFINE(DT_INST_CHILD(inst, child), child##inst, child)), \
Dregulator_max20335.c358 COND_CODE_1(DT_NODE_EXISTS(DT_INST_CHILD(inst, child)), \
359 (REGULATOR_MAX20335_DEFINE(DT_INST_CHILD(inst, child), \
Dregulator_pf1550.c412 DT_NODE_EXISTS(DT_INST_CHILD(inst, child)), \
413 (REGULATOR_PF1550_DEFINE(DT_INST_CHILD(inst, child), child##inst, child, source)), \
Dregulator_da1469x.c475 COND_CODE_1(DT_NODE_EXISTS(DT_INST_CHILD(inst, child)), \
477 DT_INST_CHILD(inst, child), child, source)), \
Dregulator_npm6001.c597 COND_CODE_1(DT_NODE_EXISTS(DT_INST_CHILD(inst, child)), \
598 (REGULATOR_NPM6001_DEFINE(DT_INST_CHILD(inst, child), child##inst, source)), \
Dregulator_pca9420.c530 COND_CODE_1(DT_NODE_EXISTS(DT_INST_CHILD(inst, child)), \
531 (REGULATOR_PCA9420_DEFINE(DT_INST_CHILD(inst, child), \
Dregulator_npm1300.c682 COND_CODE_1(DT_NODE_EXISTS(DT_INST_CHILD(inst, child)), \
683 (REGULATOR_NPM1300_DEFINE(DT_INST_CHILD(inst, child), child##inst, source)), \
Dregulator_npm2100.c762 COND_CODE_1(DT_NODE_EXISTS(DT_INST_CHILD(inst, child)), \
763 (REGULATOR_NPM2100_DEFINE(DT_INST_CHILD(inst, child), child##inst, source)), \
/Zephyr-latest/drivers/clock_control/
Dclock_control_mcux_scg_k4.c22 #define MCUX_SCG_CLOCK_NODE(name) DT_INST_CHILD(0, name)
Dclock_control_mcux_scg.c22 #define MCUX_SCG_CLOCK_NODE(name) DT_INST_CHILD(0, name)
/Zephyr-latest/drivers/gpio/
Dgpio_xlnx_axi.c384 UTIL_AND(DT_NODE_HAS_COMPAT(DT_INST_CHILD(n, gpio2), xlnx_xps_gpio_1_00_a_gpio2), \
385 DT_NODE_HAS_STATUS_OKAY(DT_INST_CHILD(n, gpio2)))
410 DEVICE_DT_DEFINE(DT_INST_CHILD(n, gpio2), &gpio_xlnx_axi_init, NULL, \
426 (.other_channel_device = DEVICE_DT_GET(DT_INST_CHILD(n, gpio2))))}; \
/Zephyr-latest/drivers/interrupt_controller/
Dintc_eirq_nxp_s32.c226 COND_CODE_1(DT_NODE_EXISTS(DT_INST_CHILD(n, irq_##idx)), \
227 (DT_PROP_OR(DT_INST_CHILD(n, irq_##idx), max_filter_counter, \
Dintc_wkpu_nxp_s32.c195 COND_CODE_1(DT_PROP(DT_INST_CHILD(n, irq_##idx), filter_enable), (BIT(idx)), (0U))
/Zephyr-latest/drivers/memc/
Dmemc_nxp_s32_qspi.c161 #define SFP_MDAD_NODE(n) DT_INST_CHILD(n, sfp_mdad)
186 #define SFP_FRAD_NODE(n) DT_INST_CHILD(n, sfp_frad)
/Zephyr-latest/drivers/misc/nxp_s32_emios/
Dnxp_s32_emios.c74 DT_FOREACH_CHILD_STATUS_OKAY(DT_INST_CHILD(n, master_bus), \
/Zephyr-latest/drivers/flash/
Dflash_simulator.c31 #define SOC_NV_FLASH_NODE DT_INST_CHILD(0, flash_0)
33 #define SOC_NV_FLASH_NODE DT_INST_CHILD(0, flash_sim_0)

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