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/Zephyr-Core-3.5.0/scripts/pylib/twister/twisterlib/
Dconfig_parser.py120 vs = v.split()
122 if len(vs) > 1:
128 return [self._cast_value(vsi, typestr[5:]) for vsi in vs]
130 return vs
138 vs = v.split()
140 if len(vs) > 1:
146 return {self._cast_value(vsi, typestr[4:]) for vsi in vs}
148 return set(vs)
/Zephyr-Core-3.5.0/subsys/net/lib/lwm2m/
Dlwm2m_senml_cbor.cddl10 vs => tstr // ; String Value
28 vs = 3
/Zephyr-Core-3.5.0/doc/hardware/peripherals/
Despi.rst13 The technical advancements include lower voltage signal levels (1.8V vs. 3.3V),
14 lower pin count, and the frequency is twice as fast (66MHz vs. 33MHz)
/Zephyr-Core-3.5.0/drivers/disk/nvme/
Dnvme_controller.c258 uint32_t cap_lo, cap_hi, to, vs, pmrcap; in nvme_controller_gather_info() local
282 vs = nvme_mmio_read_4(regs, vs); in nvme_controller_gather_info()
283 LOG_DBG("Version: 0x%08x: %d.%d", vs, in nvme_controller_gather_info()
284 NVME_MAJOR(vs), NVME_MINOR(vs)); in nvme_controller_gather_info()
Dnvme.h17 uint32_t vs; /* version */ member
335 uint8_t vs[1024]; member
/Zephyr-Core-3.5.0/boards/shields/st_b_lcd40_dsi1_mb1166/boards/
Dstm32h747i_disco_m7.overlay65 vs-active-high;
/Zephyr-Core-3.5.0/doc/build/dts/
Dindex.rst34 dt-vs-kconfig.rst
/Zephyr-Core-3.5.0/boards/common/
Dopenocd-nrf5.board.cmake3 # Infer nrf51 vs nrf52 etc from the BOARD name. This enforces a board
/Zephyr-Core-3.5.0/doc/kernel/data_structures/
Ddlist.rst48 implementation that has zero overhead vs. the normal list processing).
64 prev/next pointers of a node vs. the list struct address.
/Zephyr-Core-3.5.0/samples/net/sockets/echo_async_select/
DREADME.rst55 the same except the header files are different for Zephyr vs POSIX, and
/Zephyr-Core-3.5.0/samples/net/sockets/echo/
DREADME.rst52 the same except the header files are different for Zephyr vs POSIX.)
/Zephyr-Core-3.5.0/dts/arm/ti/
Dcc32xx.dtsi18 /* Note: Zephyr uses exception numbers, vs the IRQ #s used by the CC32XX SDK */
/Zephyr-Core-3.5.0/samples/net/sockets/echo_async/
DREADME.rst57 the same except the header files are different for Zephyr vs POSIX, and
/Zephyr-Core-3.5.0/samples/net/sockets/dumb_http_server/
DREADME.rst65 the same except the header files are different for Zephyr vs POSIX.)
/Zephyr-Core-3.5.0/dts/arm/nxp/
Dnxp_rt1060.dtsi10 * FlexRAM mapped at 0x20280000 (vs 0x20280000 on rt1050) and is
/Zephyr-Core-3.5.0/samples/net/sockets/http_get/
DREADME.rst77 the same except the header files are different for Zephyr vs POSIX.)
/Zephyr-Core-3.5.0/cmake/linker_script/common/
Dcommon-ram.cmake4 # ld align has been changed to subalign to provide identical behavior scatter vs. ld.
Dcommon-rom.cmake14 # ld align has been changed to subalign to provide identical behavior scatter vs. ld.
/Zephyr-Core-3.5.0/arch/x86/zefi/
DREADME.txt22 binary into memory and copy it vs. a bootloader like grub that will
/Zephyr-Core-3.5.0/boards/posix/native_sim/doc/
Dindex.rst106 .. csv-table:: Drivers/backends vs libC choice
/Zephyr-Core-3.5.0/doc/connectivity/networking/
Dnet-stack-architecture.rst163 (:ref:`kernel <kernel_api>` vs. :ref:`userspace <usermode_api>`) and with different
/Zephyr-Core-3.5.0/doc/develop/west/
Dbasics.rst92 :ref:`are conceptually different <modules-vs-projects>`.
/Zephyr-Core-3.5.0/boards/posix/doc/
Dbsim_boards_design.rst64 :ref:`comparison of what the POSIX arch provides vs other options<posix_arch_compare>`.
156 Overall architecture in a Zephyr application in an embedded target vs a bsim
/Zephyr-Core-3.5.0/doc/releases/
Drelease-notes-1.7.rst279 * ``ZEP-1347`` - sys_bitfield_*() take unsigned long* vs memaddr_t
313 * ``ZEP-1440`` - Kconfig choice for MINIMAL_LIBC vs NEWLIB_LIBC is not selectable
/Zephyr-Core-3.5.0/doc/contribute/
Dexternal.rst240 :ref:`modules-vs-projects` for additional information on the differences.

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