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Searched refs:reg_base (Results 1 – 24 of 24) sorted by relevance

/Zephyr-Core-3.5.0/drivers/i2c/
Di2c_dw.c60 uint32_t reg_base = get_regs(dev); in i2c_dw_enable_idma() local
63 write_dma_cr(DW_IC_DMA_ENABLE, reg_base); in i2c_dw_enable_idma()
64 reg = sys_read32(reg_base + DW_IC_REG_DMA_CR); in i2c_dw_enable_idma()
66 reg = read_dma_cr(reg_base); in i2c_dw_enable_idma()
68 write_dma_cr(reg, reg_base); in i2c_dw_enable_idma()
69 reg = sys_read32(reg_base + DW_IC_REG_DMA_CR); in i2c_dw_enable_idma()
91 uint32_t reg_base = get_regs(dev); in i2c_dw_set_fifo_th() local
93 write_tdlr(fifo_depth, reg_base); in i2c_dw_set_fifo_th()
94 write_rdlr(fifo_depth - 1, reg_base); in i2c_dw_set_fifo_th()
206 uint32_t reg_base = get_regs(dev); in i2c_dw_data_ask() local
[all …]
/Zephyr-Core-3.5.0/drivers/serial/
Duart_xlnx_ps.c180 static void xlnx_ps_disable_uart(uintptr_t reg_base) in xlnx_ps_disable_uart() argument
182 uint32_t reg_val = sys_read32(reg_base + XUARTPS_CR_OFFSET); in xlnx_ps_disable_uart()
187 sys_write32(reg_val, reg_base + XUARTPS_CR_OFFSET); in xlnx_ps_disable_uart()
204 static void xlnx_ps_enable_uart(uintptr_t reg_base) in xlnx_ps_enable_uart() argument
206 uint32_t reg_val = sys_read32(reg_base + XUARTPS_CR_OFFSET); in xlnx_ps_enable_uart()
211 sys_write32(reg_val, reg_base + XUARTPS_CR_OFFSET); in xlnx_ps_enable_uart()
233 uintptr_t reg_base = DEVICE_MMIO_GET(dev); in set_baudrate() local
268 sys_write32(divisor, reg_base + XUARTPS_BAUDDIV_OFFSET); in set_baudrate()
269 sys_write32(generator, reg_base + XUARTPS_BAUDGEN_OFFSET); in set_baudrate()
291 uintptr_t reg_base = DEVICE_MMIO_GET(dev); in uart_xlnx_ps_init() local
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/Zephyr-Core-3.5.0/drivers/counter/
Dcounter_dw_timer.c87 uintptr_t reg_base = DEVICE_MMIO_NAMED_GET(timer_dev, timer_mmio); in counter_dw_timer_irq_handler() local
93 sys_read32(reg_base + EOI_OFST); in counter_dw_timer_irq_handler()
103 sys_set_bit(reg_base + CONTROLREG_OFST, TIMER_INTR_MASK_BIT); in counter_dw_timer_irq_handler()
117 uintptr_t reg_base = DEVICE_MMIO_NAMED_GET(dev, timer_mmio); in counter_dw_timer_start() local
120 sys_clear_bit(reg_base + CONTROLREG_OFST, TIMER_CONTROL_ENABLE_BIT); in counter_dw_timer_start()
123 sys_clear_bit(reg_base + CONTROLREG_OFST, TIMER_MODE_BIT); in counter_dw_timer_start()
124 sys_set_bit(reg_base + CONTROLREG_OFST, TIMER_INTR_MASK_BIT); in counter_dw_timer_start()
125 sys_write32(FREE_RUNNING_MODE_VAL, reg_base + LOADCOUNT_OFST); in counter_dw_timer_start()
128 sys_set_bit(reg_base + CONTROLREG_OFST, TIMER_CONTROL_ENABLE_BIT); in counter_dw_timer_start()
134 uintptr_t reg_base = DEVICE_MMIO_NAMED_GET(dev, timer_mmio); in counter_dw_timer_disable() local
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/Zephyr-Core-3.5.0/drivers/gpio/
Dgpio_altera_pio.c24 uintptr_t reg_base; member
44 uintptr_t reg_base = cfg->reg_base; in gpio_pin_direction() local
57 addr = reg_base + ALTERA_AVALON_PIO_DIRECTION_OFFSET; in gpio_pin_direction()
75 uintptr_t reg_base = cfg->reg_base; in gpio_altera_configure() local
89 addr = reg_base + ALTERA_AVALON_PIO_DIRECTION_OFFSET; in gpio_altera_configure()
109 uintptr_t reg_base = cfg->reg_base; in gpio_altera_port_get_raw() local
112 addr = reg_base + ALTERA_AVALON_PIO_DATA_OFFSET; in gpio_altera_port_get_raw()
129 uintptr_t reg_base = cfg->reg_base; in gpio_altera_port_set_bits_raw() local
144 addr = reg_base + ALTERA_AVALON_PIO_SET_BITS; in gpio_altera_port_set_bits_raw()
147 addr = reg_base + ALTERA_AVALON_PIO_DATA_OFFSET; in gpio_altera_port_set_bits_raw()
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Dgpio_rcar.c30 DEVICE_MMIO_NAMED_ROM(reg_base);
38 DEVICE_MMIO_NAMED_RAM(reg_base);
58 return sys_read32(DEVICE_MMIO_NAMED_GET(dev, reg_base) + offs); in gpio_rcar_read()
63 sys_write32(value, DEVICE_MMIO_NAMED_GET(dev, reg_base) + offs); in gpio_rcar_write()
254 DEVICE_MMIO_NAMED_MAP(dev, reg_base, K_MEM_CACHE_NONE); in gpio_rcar_init()
283 DEVICE_MMIO_NAMED_ROM_INIT(reg_base, DT_DRV_INST(n)), \
Dgpio_intel.c100 DEVICE_MMIO_NAMED_ROM(reg_base);
111 DEVICE_MMIO_NAMED_RAM(reg_base);
121 return GPIO_REG_BASE(DEVICE_MMIO_NAMED_GET(dev, reg_base)); in regs()
126 return GPIO_PAD_BASE(DEVICE_MMIO_NAMED_GET(dev, reg_base)); in pad_base()
545 device_map(&data->reg_base, in gpio_intel_init()
546 cfg->reg_base.phys_addr & ~0xFFU, in gpio_intel_init()
547 cfg->reg_base.size, in gpio_intel_init()
550 DEVICE_MMIO_NAMED_MAP(dev, reg_base, K_MEM_CACHE_NONE); in gpio_intel_init()
584 DEVICE_MMIO_NAMED_ROM_INIT(reg_base, DT_DRV_INST(n)), \
Dgpio_ite_it8xxx2_v2.c316 volatile uint8_t *reg_base = in gpio_ite_isr() local
318 volatile uint8_t *reg_wuesr = reg_base + 1; in gpio_ite_isr()
363 volatile uint8_t *reg_base = (uint8_t *)gpio_config->wuc_base[pin]; local
364 volatile uint8_t *reg_wuemr = reg_base;
365 volatile uint8_t *reg_wuesr = reg_base + 1;
366 volatile uint8_t *reg_wubemr = reg_base + 3;
/Zephyr-Core-3.5.0/soc/x86/raptor_lake/
Dsoc_gpio.h28 #define GPIO_REG_BASE(reg_base) \ argument
29 (reg_base & ~PAD_BASE_ADDR_MASK)
31 #define GPIO_PAD_BASE(reg_base) \ argument
32 (reg_base & PAD_BASE_ADDR_MASK)
/Zephyr-Core-3.5.0/soc/x86/elkhart_lake/
Dsoc_gpio.h29 #define GPIO_REG_BASE(reg_base) \ argument
30 (reg_base & ~PAD_BASE_ADDR_MASK)
32 #define GPIO_PAD_BASE(reg_base) \ argument
33 (reg_base & PAD_BASE_ADDR_MASK)
/Zephyr-Core-3.5.0/soc/x86/alder_lake/
Dsoc_gpio.h29 #define GPIO_REG_BASE(reg_base) \ argument
30 (reg_base & ~PAD_BASE_ADDR_MASK)
32 #define GPIO_PAD_BASE(reg_base) \ argument
33 (reg_base & PAD_BASE_ADDR_MASK)
/Zephyr-Core-3.5.0/drivers/flash/
Dflash_cadence_qspi_nor_ll.c23 return (sys_read32(cad_params->reg_base + CAD_QSPI_CFG) & CAD_QSPI_CFG_IDLE) >> 31; in cad_qspi_idle()
37 sys_clear_bits(cad_params->reg_base + CAD_QSPI_CFG, ~CAD_QSPI_CFG_BAUDDIV_MSK); in cad_qspi_set_baudrate_div()
39 sys_set_bits(cad_params->reg_base + CAD_QSPI_CFG, CAD_QSPI_CFG_BAUDDIV(div)); in cad_qspi_set_baudrate_div()
55 cad_params->reg_base + CAD_QSPI_DEVSZ); in cad_qspi_configure_dev_size()
72 cad_params->reg_base + CAD_QSPI_DEVRD); in cad_qspi_set_read_config()
88 cad_params->reg_base + CAD_QSPI_DEVWR); in cad_qspi_set_write_config()
102 uint32_t cfg = sys_read32(cad_params->reg_base + CAD_QSPI_CFG); in cad_qspi_timing_config()
107 sys_write32(cfg, cad_params->reg_base + CAD_QSPI_CFG); in cad_qspi_timing_config()
111 cad_params->reg_base + CAD_QSPI_DELAY); in cad_qspi_timing_config()
126 sys_write32((sys_read32(cad_params->reg_base + CAD_QSPI_CFG) & CAD_QSPI_CFG_CS_MSK) | in cad_qspi_stig_cmd_helper()
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Dflash_cadence_qspi_nor.c128 cad_params->reg_base = DEVICE_MMIO_NAMED_GET(dev, qspi_reg); in flash_cad_init()
Dflash_cadence_qspi_nor_ll.h165 uintptr_t reg_base; member
/Zephyr-Core-3.5.0/drivers/pwm/
Dpwm_intel_blinky.c26 DEVICE_MMIO_NAMED_ROM(reg_base);
33 DEVICE_MMIO_NAMED_RAM(reg_base);
78 sys_write32(val, rt->reg_base + cfg->reg_offset); in bk_intel_set_cycles()
107 device_map(&runtime->reg_base, in bk_intel_init()
108 config->reg_base.phys_addr & ~0xFFU, in bk_intel_init()
109 config->reg_base.size, in bk_intel_init()
117 DEVICE_MMIO_NAMED_ROM_INIT(reg_base, DT_DRV_INST(n)), \
/Zephyr-Core-3.5.0/drivers/watchdog/
Dwdt_opentitan.c90 volatile uintptr_t reg_base = dev_cfg->regs; in ot_aontimer_install_timeout() local
115 if (!sys_read32(reg_base + OT_REG_WDOG_REGWEN_OFFSET)) { in ot_aontimer_install_timeout()
121 if (sys_read32(reg_base + OT_REG_WDOG_CTRL_OFFSET) & BIT(0)) { in ot_aontimer_install_timeout()
137 sys_write32((uint32_t) bark_thold, reg_base + OT_REG_WDOG_BARK_THOLD_OFFSET); in ot_aontimer_install_timeout()
138 sys_write32((uint32_t) bite_thold, reg_base + OT_REG_WDOG_BITE_THOLD_OFFSET); in ot_aontimer_install_timeout()
147 sys_write32((uint32_t) bite_thold, reg_base + OT_REG_WDOG_BARK_THOLD_OFFSET); in ot_aontimer_install_timeout()
149 sys_write32(UINT32_MAX, reg_base + OT_REG_WDOG_BITE_THOLD_OFFSET); in ot_aontimer_install_timeout()
154 sys_write32(UINT32_MAX, reg_base + OT_REG_WDOG_BARK_THOLD_OFFSET); in ot_aontimer_install_timeout()
155 sys_write32((uint32_t) bite_thold, reg_base + OT_REG_WDOG_BITE_THOLD_OFFSET); in ot_aontimer_install_timeout()
/Zephyr-Core-3.5.0/drivers/misc/timeaware_gpio/
Dtimeaware_gpio_intel.c53 DEVICE_MMIO_NAMED_ROM(reg_base);
59 DEVICE_MMIO_NAMED_RAM(reg_base);
64 return DEVICE_MMIO_NAMED_GET(dev, reg_base); in regs()
205 device_map(&rt->reg_base, in tgpio_init()
206 cfg->reg_base.phys_addr & ~0xFFU, in tgpio_init()
207 cfg->reg_base.size, in tgpio_init()
216 DEVICE_MMIO_NAMED_ROM_INIT(reg_base, DT_DRV_INST(n)), \
/Zephyr-Core-3.5.0/drivers/peci/
Dpeci_ite_it8xxx2.c118 static void peci_it8xxx2_init_vtts(struct peci_it8xxx2_regs *reg_base, in peci_it8xxx2_init_vtts() argument
121 reg_base->PADCTLR = (reg_base->PADCTLR & PECI_DVIE) | vol_opt; in peci_it8xxx2_init_vtts()
124 static void peci_it8xxx2_rst_status(struct peci_it8xxx2_regs *reg_base) in peci_it8xxx2_rst_status() argument
126 reg_base->HOSTAR = HOSTAR_RST_ANYBIT; in peci_it8xxx2_rst_status()
129 static int peci_it8xxx2_check_host_busy(struct peci_it8xxx2_regs *reg_base) in peci_it8xxx2_check_host_busy() argument
131 return (reg_base->HOSTAR & HOBY) ? (-EBUSY) : 0; in peci_it8xxx2_check_host_busy()
/Zephyr-Core-3.5.0/drivers/dma/
Ddma_pl330.c262 uint32_t reg_base, int ch, int secure) in dma_pl330_start_dma_ch() argument
271 data = sys_read32(reg_base + DMAC_PL330_DBGSTATUS); in dma_pl330_start_dma_ch()
281 reg_base + DMAC_PL330_DBGINST0); in dma_pl330_start_dma_ch()
284 reg_base + DMAC_PL330_DBGINST1); in dma_pl330_start_dma_ch()
286 sys_write32(0x0, reg_base + DMAC_PL330_DBGCMD); in dma_pl330_start_dma_ch()
290 data = sys_read32(reg_base + DMAC_PL330_DBGCMD); in dma_pl330_start_dma_ch()
300 static int dma_pl330_wait(uint32_t reg_base, int ch) in dma_pl330_wait() argument
303 uint32_t cs0_reg = reg_base + DMAC_PL330_CS0; in dma_pl330_wait()
358 ret = dma_pl330_start_dma_ch(dev, dev_cfg->reg_base, channel, in dma_pl330_xfer()
365 ret = dma_pl330_wait(dev_cfg->reg_base, channel); in dma_pl330_xfer()
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Ddma_pl330.h163 mem_addr_t reg_base; member
/Zephyr-Core-3.5.0/soc/x86/apollo_lake/
Dsoc_gpio.h293 #define GPIO_REG_BASE(reg_base) reg_base argument
295 #define GPIO_PAD_BASE(reg_base) \ argument
296 (sys_read32(reg_base + REG_PAD_BASE_ADDR))
/Zephyr-Core-3.5.0/drivers/dai/intel/dmic/
Ddmic.c118 uint32_t dest = dmic->reg_base + reg; in dai_dmic_update_bits()
121 dmic->reg_base, reg, mask, val); in dai_dmic_update_bits()
129 sys_write32(val, dmic->reg_base + reg); in dai_dmic_write()
135 return sys_read32(dmic->reg_base + reg); in dai_dmic_read()
912 .reg_base = DT_INST_REG_ADDR_BY_IDX(n, 0), \
Ddmic.h174 uint32_t reg_base; member
Ddmic_nhlt.c29 sys_write32(val, dmic->reg_base + reg); in dai_dmic_write()
34 return sys_read32(dmic->reg_base + reg); in dai_dmic_read()
/Zephyr-Core-3.5.0/drivers/espi/
Despi_mchp_xec_host_v2.c84 uint32_t reg_base; /* logical device registers */ member