60 	uint32_t reg_base = get_regs(dev);  in i2c_dw_enable_idma()  local
63 		write_dma_cr(DW_IC_DMA_ENABLE, reg_base);  in i2c_dw_enable_idma()
64 		reg = sys_read32(reg_base + DW_IC_REG_DMA_CR);  in i2c_dw_enable_idma()
66 		reg = read_dma_cr(reg_base);  in i2c_dw_enable_idma()
68 		write_dma_cr(reg, reg_base);  in i2c_dw_enable_idma()
69 		reg = sys_read32(reg_base + DW_IC_REG_DMA_CR);  in i2c_dw_enable_idma()
91 	uint32_t reg_base = get_regs(dev);  in i2c_dw_set_fifo_th()  local
93 	write_tdlr(fifo_depth, reg_base);  in i2c_dw_set_fifo_th()
94 	write_rdlr(fifo_depth - 1, reg_base);  in i2c_dw_set_fifo_th()
206 	uint32_t reg_base = get_regs(dev);  in i2c_dw_data_ask()  local
210 		clear_bit_intr_mask_tx_empty(reg_base);  in i2c_dw_data_ask()
215 	ic_comp_param_1.raw = read_comp_param_1(reg_base);  in i2c_dw_data_ask()
220 	rx_empty = (rx_buffer_depth - read_rxflr(reg_base)) - dw->rx_pending;  in i2c_dw_data_ask()
230 	tx_empty = tx_buffer_depth - read_txflr(reg_base);  in i2c_dw_data_ask()
252 		clear_bit_intr_mask_tx_empty(reg_base);  in i2c_dw_data_ask()
254 		write_cmd_data(data, reg_base);  in i2c_dw_data_ask()
266 	uint32_t reg_base = get_regs(dev);  in i2c_dw_data_read()  local
269 	if (test_bit_status_rfne(reg_base) && (dw->xfr_len > 0)) {  in i2c_dw_data_read()
275 	while (test_bit_status_rfne(reg_base) && (dw->xfr_len > 0)) {  in i2c_dw_data_read()
276 		dw->xfr_buf[0] = (uint8_t)read_cmd_data(reg_base);  in i2c_dw_data_read()
299 	uint32_t reg_base = get_regs(dev);  in i2c_dw_data_send()  local
303 		clear_bit_intr_mask_tx_empty(reg_base);  in i2c_dw_data_send()
310 	while (test_bit_status_tfnt(reg_base) && (dw->xfr_len > 0)) {  in i2c_dw_data_send()
328 		write_cmd_data(data, reg_base);  in i2c_dw_data_send()
333 		if (test_bit_intr_stat_tx_abrt(reg_base)) {  in i2c_dw_data_send()
345 	uint32_t reg_base = get_regs(dev);  in i2c_dw_transfer_complete()  local
347 	write_intr_mask(DW_DISABLE_ALL_I2C_INT, reg_base);  in i2c_dw_transfer_complete()
348 	value = read_clr_intr(reg_base);  in i2c_dw_transfer_complete()
365 	uint32_t reg_base = get_regs(port);  in i2c_dw_isr()  local
370 	intr_stat.raw = read_intr_stat(reg_base);  in i2c_dw_isr()
388 	if (test_bit_con_master_mode(reg_base)) {  in i2c_dw_isr()
390 		uint32_t stat = sys_read32(reg_base + IDMA_REG_INTR_STS);  in i2c_dw_isr()
418 			set_bit_intr_mask_tx_empty(reg_base);  in i2c_dw_isr()
442 			value = read_clr_stop_det(reg_base);  in i2c_dw_isr()
449 		uint32_t slave_activity = test_bit_status_activity(reg_base);  in i2c_dw_isr()
469 				read_clr_rd_req(reg_base);  in i2c_dw_isr()
496 	uint32_t reg_base = get_regs(dev);  in i2c_dw_setup()  local
501 	clear_bit_enable_en(reg_base);  in i2c_dw_setup()
504 	write_intr_mask(0, reg_base);  in i2c_dw_setup()
507 	value = read_clr_intr(reg_base);  in i2c_dw_setup()
535 		write_ss_scl_lcnt(dw->lcnt, reg_base);  in i2c_dw_setup()
536 		write_ss_scl_hcnt(dw->hcnt, reg_base);  in i2c_dw_setup()
544 		write_fs_scl_lcnt(dw->lcnt, reg_base);  in i2c_dw_setup()
545 		write_fs_scl_hcnt(dw->hcnt, reg_base);  in i2c_dw_setup()
555 		write_hs_scl_lcnt(dw->lcnt, reg_base);  in i2c_dw_setup()
556 		write_hs_scl_hcnt(dw->hcnt, reg_base);  in i2c_dw_setup()
569 	write_con(ic_con.raw, reg_base);  in i2c_dw_setup()
577 	write_rx_tl(0, reg_base);  in i2c_dw_setup()
587 	write_tx_tl(0, reg_base);  in i2c_dw_setup()
589 	ic_tar.raw = read_tar(reg_base);  in i2c_dw_setup()
591 	if (test_bit_con_master_mode(reg_base)) {  in i2c_dw_setup()
596 		write_sar(slave_address, reg_base);  in i2c_dw_setup()
612 	write_tar(ic_tar.raw, reg_base);  in i2c_dw_setup()
626 	uint32_t reg_base = get_regs(dev);  in i2c_dw_transfer()  local
639 	if (test_bit_status_activity(reg_base) || (dw->state & I2C_DW_BUSY)) {  in i2c_dw_transfer()
652 	set_bit_enable_en(reg_base);  in i2c_dw_transfer()
699 		if (test_bit_con_master_mode(reg_base)) {  in i2c_dw_transfer()
702 						  DW_ENABLE_RX_INT_I2C_MASTER), reg_base);  in i2c_dw_transfer()
705 			write_intr_mask(DW_ENABLE_TX_INT_I2C_SLAVE, reg_base);  in i2c_dw_transfer()
740 	uint32_t reg_base = get_regs(dev);  in i2c_dw_runtime_configure()  local
751 		if (I2C_STD_LCNT <= (read_fs_spklen(reg_base) + 7)) {  in i2c_dw_runtime_configure()
752 			value = read_fs_spklen(reg_base) + 8;  in i2c_dw_runtime_configure()
762 		if (I2C_STD_HCNT <= (read_fs_spklen(reg_base) + 5)) {  in i2c_dw_runtime_configure()
763 			value = read_fs_spklen(reg_base) + 6;  in i2c_dw_runtime_configure()
777 		if (I2C_FS_LCNT <= (read_fs_spklen(reg_base) + 7)) {  in i2c_dw_runtime_configure()
778 			value = read_fs_spklen(reg_base) + 8;  in i2c_dw_runtime_configure()
789 		if (I2C_FS_HCNT <= (read_fs_spklen(reg_base) + 5)) {  in i2c_dw_runtime_configure()
790 			value = read_fs_spklen(reg_base) + 6;  in i2c_dw_runtime_configure()
799 			if (I2C_HS_LCNT <= (read_hs_spklen(reg_base) + 7)) {  in i2c_dw_runtime_configure()
800 				value = read_hs_spklen(reg_base) + 8;  in i2c_dw_runtime_configure()
807 			if (I2C_HS_HCNT <= (read_hs_spklen(reg_base) + 5)) {  in i2c_dw_runtime_configure()
808 				value = read_hs_spklen(reg_base) + 6;  in i2c_dw_runtime_configure()
826 	value = read_clr_intr(reg_base);  in i2c_dw_runtime_configure()
841 	uint32_t reg_base = get_regs(dev);  in i2c_dw_read_byte_non_blocking()  local
843 	if (!test_bit_status_rfne(reg_base)) { /* Rx FIFO must not be empty */  in i2c_dw_read_byte_non_blocking()
847 	return (uint8_t)read_cmd_data(reg_base);  in i2c_dw_read_byte_non_blocking()
852 	uint32_t reg_base = get_regs(dev);  in i2c_dw_write_byte_non_blocking()  local
854 	if (!test_bit_status_tfnt(reg_base)) { /* Tx FIFO must not be full */  in i2c_dw_write_byte_non_blocking()
858 	write_cmd_data(data, reg_base);  in i2c_dw_write_byte_non_blocking()
864 	uint32_t reg_base = get_regs(dev);  in i2c_dw_set_master_mode()  local
867 	clear_bit_enable_en(reg_base);  in i2c_dw_set_master_mode()
872 	write_con(ic_con.raw, reg_base);  in i2c_dw_set_master_mode()
874 	set_bit_enable_en(reg_base);  in i2c_dw_set_master_mode()
876 	ic_comp_param_1.raw = read_comp_param_1(reg_base);  in i2c_dw_set_master_mode()
878 	write_tx_tl(ic_comp_param_1.bits.tx_buffer_depth + 1, reg_base);  in i2c_dw_set_master_mode()
879 	write_rx_tl(ic_comp_param_1.bits.rx_buffer_depth + 1, reg_base);  in i2c_dw_set_master_mode()
886 	uint32_t reg_base = get_regs(dev);  in i2c_dw_set_slave_mode()  local
889 	ic_con.raw = read_con(reg_base);  in i2c_dw_set_slave_mode()
891 	clear_bit_enable_en(reg_base);  in i2c_dw_set_slave_mode()
899 	write_con(ic_con.raw, reg_base);  in i2c_dw_set_slave_mode()
900 	write_sar(addr, reg_base);  in i2c_dw_set_slave_mode()
901 	write_intr_mask(~DW_INTR_MASK_RESET, reg_base);  in i2c_dw_set_slave_mode()
903 	set_bit_enable_en(reg_base);  in i2c_dw_set_slave_mode()
905 	write_tx_tl(0, reg_base);  in i2c_dw_set_slave_mode()
906 	write_rx_tl(0, reg_base);  in i2c_dw_set_slave_mode()
917 	uint32_t reg_base = get_regs(dev);  in i2c_dw_slave_register()  local
926 			DW_INTR_MASK_START_DET, reg_base);  in i2c_dw_slave_register()
947 	uint32_t reg_base = get_regs(dev);  in i2c_dw_slave_read_clear_intr_bits()  local
951 	intr_stat.raw = read_intr_stat(reg_base);  in i2c_dw_slave_read_clear_intr_bits()
954 		read_clr_tx_abrt(reg_base);  in i2c_dw_slave_read_clear_intr_bits()
959 		read_clr_rx_under(reg_base);  in i2c_dw_slave_read_clear_intr_bits()
964 		read_clr_rx_over(reg_base);  in i2c_dw_slave_read_clear_intr_bits()
969 		read_clr_tx_over(reg_base);  in i2c_dw_slave_read_clear_intr_bits()
974 		read_clr_rx_done(reg_base);  in i2c_dw_slave_read_clear_intr_bits()
979 		read_clr_activity(reg_base);  in i2c_dw_slave_read_clear_intr_bits()
984 		read_clr_stop_det(reg_base);  in i2c_dw_slave_read_clear_intr_bits()
992 		read_clr_start_det(reg_base);  in i2c_dw_slave_read_clear_intr_bits()
997 		read_clr_gen_call(reg_base);  in i2c_dw_slave_read_clear_intr_bits()
1077 	uint32_t reg_base = get_regs(dev);  in i2c_dw_initialize()  local
1079 	clear_bit_enable_en(reg_base);  in i2c_dw_initialize()
1082 	if (read_comp_type(reg_base) != I2C_DW_MAGIC_KEY) {  in i2c_dw_initialize()
1093 	ic_con.raw = read_con(reg_base);  in i2c_dw_initialize()