Home
last modified time | relevance | path

Searched refs:r0 (Results 1 – 25 of 76) sorted by relevance

1234

/Zephyr-Core-3.5.0/arch/arm/core/
Duserspace.S48 mov lr, r0
51 ldr r0, =_kernel
52 ldr r0, [r0, #_kernel_offset_to_current]
57 ldr r0, [r0, r1] /* priv stack ptr */
59 add r0, r0, r1
63 ldr r0, [r0, #_thread_offset_to_priv_stack_start] /* priv stack ptr */
65 add r0, r0, ip
67 ldr r0, [r0, #_thread_offset_to_priv_stack_start] /* priv stack ptr */
69 add r0, r0, ip
73 str r0, [ip, #_thread_offset_to_priv_stack_end] /* priv stack end */
[all …]
/Zephyr-Core-3.5.0/arch/arm/core/cortex_a_r/
Disr_wrapper.S51 push {r0}
55 mrs r0, spsr
56 and r0, #MODE_MASK
57 cmp r0, #MODE_USR
60 ldr r0, =_kernel
61 ldr r0, [r0, #_kernel_offset_to_current]
65 str sp, [r0, #_thread_offset_to_sp_usr] /* sp_usr */
68 ldr sp, [r0, #_thread_offset_to_priv_stack_end] /* priv stack end */
72 pop {r0}
85 push {r0-r3, r12, lr}
[all …]
Dswap_helper.S47 push {r0, lr}
49 pop {r0, lr}
62 ldr r0, =_thread_offset_to_callee_saved
63 add r0, r2
67 stm r0, {r4-r11, sp}
71 ldrb r0, [r2, #_thread_offset_to_user_options]
72 tst r0, #K_FP_REGS /* _current->base.user_options & K_FP_REGS */
84 ldr r0, [r1, #_kernel_offset_to_fp_ctx]
85 cmp r0, #0
88 vstmia r0!, {s0-s15}
[all …]
Dexc_exit.S33 push {r0-r1}
43 pop {r0-r1}
46 str r0, [sp, #8]
55 ldr r0, =_kernel
56 ldr r0, [r0, #_kernel_offset_to_current]
58 ldr sp, [r0, #_thread_offset_to_sp_usr] /* sp_usr */
61 pop {r0-r1}
80 cmp r0, #0
144 ldr r0, [r3, #_kernel_offset_to_nested]
145 cmp r0, #1
[all …]
Dexc.S50 stmfd sp, {r0-r3, r12, lr}^
57 mov r0, #FPEXC_EN
58 vmsr fpexc, r0
59 vmrs r0, fpscr
66 stm r2, {r0, r1}
72 mov r0, #0
73 str r0, [sp, #4]
74 str r0, [sp, #8]
82 mov r0, sp
85 mov r0, sp
[all …]
Dreset.S51 mrs r0, cpsr
52 and r0, r0, #MODE_MASK
53 cmp r0, #MODE_HYP
57 ldr r0, =(HSCTLR_RES1 | SCTLR_I_BIT | SCTLR_C_BIT)
58 mcr p15, 4, r0, c1, c0, 0
61 ldr r0, =HACTLR_INIT
62 mcr p15, 4, r0, c1, c0, 1
65 mrs r0, cpsr
66 bic r0, #MODE_MASK
67 orr r0, #MODE_SVC
[all …]
Dcpu_idle.S27 push {r0, lr}
30 cmp r0, #0
48 pop {r0, lr}
54 push {r0, lr}
56 pop {r0, lr}
73 push {r0, lr}
75 pop {r0, lr}
90 cmp r0, #0
/Zephyr-Core-3.5.0/arch/arc/core/
Dreset.S52 mov_s r0, 0
53 kflag r0
56 sflag r0
61 sr r0, [_ARC_V2_AUX_IRQ_ACT]
62 sr r0, [_ARC_V2_AUX_IRQ_CTRL]
64 sr r0, [_ARC_V2_AUX_IRQ_HINT]
69 MOVR r0, _VectorTable
71 sr r0, [_ARC_V2_IRQ_VECT_BASE_S]
73 SRR r0, [_ARC_V2_IRQ_VECT_BASE]
76 lr r0, [_ARC_V2_STATUS32]
[all …]
Duserspace.S66 pop_s r0
72 st.aw r0, [r5, -4]
107 push_s r0
118 mov_s r0, 0xaaaaaaaa
120 mov_s r0, 0x0
123 st.ab r0, [r4, 4]
136 _enable_stack_checking r0
144 lr r0, [_ARC_V2_STATUS32]
145 bset r0, r0, _ARC_V2_STATUS32_U_BIT
149 sr r0, [_ARC_V2_ERSTATUS]
[all …]
Disr_wrapper.S212 push r0
214 lr r0, [_ARC_V2_AUX_IRQ_ACT]
215 ffs r0, r0
216 cmp r0, 0
219 pop r0
222 lr r0, [_ARC_V2_STATUS32_P0]
223 st_s r0, [sp, ___isf_t_status32_OFFSET]
250 clri r0 /* do not interrupt exiting tickless idle operations */
260 seti r0
290 lr r0, [_ARC_V2_ICAUSE]
[all …]
Dfast_irq.S78 _check_and_inc_int_nest_counter r0, r1
81 mov_s r0, sp
125 push_s r0
142 _dec_int_nest_counter r0, r1
144 _check_nest_int_by_irq_act r0, r1
154 CMPR r0, 0
183 st r0, [r1, -4]
205 lr r0, [_ARC_V2_AUX_IRQ_ACT]
206 bbit0 r0, 31, _firq_from_kernel
208 lr r0, [_ARC_V2_STATUS32]
[all …]
Dfault_s.S41 lr r0,[_ARC_V2_ERSEC_STAT]
42 st_s r0, [sp, ___isf_t_sec_stat_OFFSET]
44 LRR r0, [_ARC_V2_ERET]
45 STR r0, sp, ___isf_t_pc_OFFSET
46 LRR r0, [_ARC_V2_ERSTATUS]
47 STR r0, sp, ___isf_t_status32_OFFSET
103 MOVR r0, sp
119 BREQR r0, 0, _exc_return_from_exc
126 MOVR r2, r0
169 mov_s r0, _ARC_V2_AUX_IRQ_ACT
[all …]
/Zephyr-Core-3.5.0/arch/arm/core/cortex_m/
Dreset.S73 movs.n r0, #0
75 strb r0, [r1]
80 movs.n r0, #0
81 msr CONTROL, r0
85 movs.n r0, #0
86 msr MSPLIM, r0
87 msr PSPLIM, r0
103 movs.n r0, #0
105 str r0, [r1]
108 ldr r0, =z_main_stack + CONFIG_MAIN_STACK_SIZE
[all …]
Dswap_helper.S59 push {r0, lr}
62 pop {r0, r1}
65 pop {r0, lr}
79 ldr r0, =_thread_offset_to_callee_saved
80 add r0, r2
87 stmea r0!, {r4-r7}
95 stmea r0!, {r3-r7}
97 stmia r0, {v1-v8, ip}
108 add r0, r2, #_thread_offset_to_preempt_float
109 vstmia r0, {s16-s31}
[all …]
Disr_wrapper.S48 push {r0,lr} /* r0, lr are now the first items on the stack */
75 ldr r0, [r2, #_kernel_offset_to_idle]
76 cmp r0, #0
100 mrs r0, IPSR /* get exception number */
103 subs r0, r1 /* get IRQ number */
104 lsls r0, #3 /* table is 8-byte wide */
106 sub r0, r0, #16 /* get IRQ number */
107 lsl r0, r0, #3 /* table is 8-byte wide */
113 add r1, r1, r0 /* table entry: ISRs must have their MSB set to stay
116 ldm r1!,{r0,r3} /* arg in r0, ISR in r3 */
[all …]
Dpm_s2ram.S77 blx r0
99 ldr r0, =marker
100 ldr r0, [r0]
102 cmp r0, r1
110 ldr r0, =marker
112 str r1, [r0]
117 ldr r0, =_cpu_context
119 ldr r1, [r0, #___cpu_context_t_msp_OFFSET]
122 ldr r1, [r0, #___cpu_context_t_msplim_OFFSET]
125 ldr r1, [r0, #___cpu_context_t_psp_OFFSET]
[all …]
Dcpu_idle.S35 push {r0, lr}
38 cmp r0, #0
57 pop {r0, r1}
60 pop {r0, lr}
86 push {r0, lr}
96 pop {r0, r1}
99 pop {r0, lr}
119 eors.n r0, r0
120 msr BASEPRI, r0
147 push {r0, lr}
[all …]
/Zephyr-Core-3.5.0/arch/arc/core/secureshield/
Darc_secure.S81 lr r0, [_ARC_V2_STATUS32]
82 and r0, r0, 0x1e
83 asr r0, r0
84 or r0, r0, 0x30
91 btst r0, 4
93 mov r0, (CONFIG_NUM_IRQ_PRIO_LEVELS - 1)
97 cmp r0, r6
98 mov.hs r0, r6
100 and r0, r0, 0xf
101 brhs r0, ARC_N_IRQ_START_LEVEL, __seti_1
[all …]
/Zephyr-Core-3.5.0/soc/arm/ti_lm3s6965/
Dreboot.S19 eors r0, r0
23 str r0, [r1, #0xd08] /* VTOR */
25 ldr r0, [r0, #4]
26 bx r0
32 ldr r0, =_SCS_ICSR_RETTOBASE
35 ands.w r0, r1
/Zephyr-Core-3.5.0/boards/arm/teensy4/
Dteensy4-pinctrl.dtsi18 drive-strength = "r0-5";
26 drive-strength = "r0-5";
40 drive-strength = "r0-6";
46 drive-strength = "r0-6";
58 drive-strength = "r0-6";
70 drive-strength = "r0-6";
82 drive-strength = "r0-6";
94 drive-strength = "r0-6";
107 drive-strength = "r0-6";
120 drive-strength = "r0-6";
[all …]
/Zephyr-Core-3.5.0/boards/arm/mimxrt1062_fmurt6/
Dmimxrt1062_fmurt6-pinctrl.dtsi17 drive-strength = "r0-6";
26 drive-strength = "r0-6";
40 drive-strength = "r0-5";
48 drive-strength = "r0-5";
54 drive-strength = "r0-5";
66 drive-strength = "r0-6";
76 drive-strength = "r0-6";
86 drive-strength = "r0-6";
97 drive-strength = "r0-7";
107 drive-strength = "r0-7";
[all …]
/Zephyr-Core-3.5.0/boards/arm/mimxrt1020_evk/
Dmimxrt1020_evk-pinctrl.dtsi17 drive-strength = "r0-6";
28 drive-strength = "r0-6";
35 drive-strength = "r0-5";
50 drive-strength = "r0-5";
58 drive-strength = "r0-5";
66 drive-strength = "r0-6";
76 drive-strength = "r0-6";
87 drive-strength = "r0-6";
99 drive-strength = "r0-6";
114 drive-strength = "r0-6";
[all …]
/Zephyr-Core-3.5.0/boards/arm/mimxrt1050_evk/
Dmimxrt1050_evk-pinctrl.dtsi18 drive-strength = "r0-6";
28 drive-strength = "r0-6";
47 drive-strength = "r0-6";
58 drive-strength = "r0-6";
66 drive-strength = "r0-5";
82 drive-strength = "r0-5";
95 drive-strength = "r0-6";
105 drive-strength = "r0-6";
115 drive-strength = "r0-4";
126 drive-strength = "r0-6";
[all …]
/Zephyr-Core-3.5.0/soc/arm/nxp_lpc/lpc54xxx/gcc/
Dstartup_LPC54114_cm4.S50 ldr r0, [r6, #0]
51 ldr r1, [r0] /* r1 = CPU ID status */
63 ldr r0, [r6, #4]
64 ldr r3, [r0] /* r3 = SYSCON co-processor CPU control status */
78 ldr r0, [r6, #8]
79 ldr r2, [r0] /* r1 = SYSCON co-processor boot address */
84 ldr r0, [r6, #12]
85 ldr r1, [r0] /* r5 = SYSCON co-processor stack address */
/Zephyr-Core-3.5.0/boards/arm/mimxrt1064_evk/
Dmimxrt1064_evk-pinctrl.dtsi18 drive-strength = "r0-6";
28 drive-strength = "r0-6";
47 drive-strength = "r0-6";
58 drive-strength = "r0-6";
66 drive-strength = "r0-5";
82 drive-strength = "r0-5";
95 drive-strength = "r0-6";
105 drive-strength = "r0-6";
115 drive-strength = "r0-6";
125 drive-strength = "r0-4";
[all …]

1234