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Searched refs:csr_read (Results 1 – 19 of 19) sorted by relevance

/Zephyr-Core-3.5.0/samples/userspace/syscall_perf/src/
Dtest_supervisor.c25 inst_before = csr_read(0xB02); in supervisor_thread_function()
26 cycle_before = csr_read(0xB00); in supervisor_thread_function()
28 cycle_count = csr_read(0xB00); in supervisor_thread_function()
29 inst_count = csr_read(0xB02); in supervisor_thread_function()
Dtest_user.c25 inst_before = csr_read(0xC02); in user_thread_function()
26 cycle_before = csr_read(0xC00); in user_thread_function()
28 cycle_count = csr_read(0xC00); in user_thread_function()
29 inst_count = csr_read(0xC02); in user_thread_function()
/Zephyr-Core-3.5.0/arch/riscv/core/
Dfpu.c65 unsigned long status = csr_read(mstatus); in z_riscv_fpu_disable()
79 __ASSERT((csr_read(mstatus) & MSTATUS_IEN) == 0, in z_riscv_fpu_load()
81 __ASSERT((csr_read(mstatus) & MSTATUS_FS) == 0, in z_riscv_fpu_load()
103 __ASSERT((csr_read(mstatus) & MSTATUS_IEN) == 0, in z_riscv_flush_local_fpu()
105 __ASSERT((csr_read(mstatus) & MSTATUS_FS) == 0, in z_riscv_flush_local_fpu()
135 __ASSERT((csr_read(mstatus) & MSTATUS_IEN) == 0, in flush_owned_fpu()
210 (csr_read(mstatus) & MSTATUS_FS) == 0, in z_riscv_fpu_trap()
256 __ASSERT((csr_read(mstatus) & MSTATUS_IEN) == 0, in fpu_access_allowed()
Dpmp.c112 #define PMPADDR_READ(x) pmp_addr[x] = csr_read(pmpaddr##x) in dump_pmp_regs()
122 pmp_cfg[0] = csr_read(pmpcfg0); in dump_pmp_regs()
124 pmp_cfg[1] = csr_read(pmpcfg2); in dump_pmp_regs()
127 pmp_cfg[0] = csr_read(pmpcfg0); in dump_pmp_regs()
128 pmp_cfg[1] = csr_read(pmpcfg1); in dump_pmp_regs()
130 pmp_cfg[2] = csr_read(pmpcfg2); in dump_pmp_regs()
131 pmp_cfg[3] = csr_read(pmpcfg3); in dump_pmp_regs()
Dirq_manage.c20 mcause = csr_read(mcause); in z_irq_spurious()
Dsmp.c100 MSIP(csr_read(mhartid)) = 0; in ipi_handler()
Dthread.c152 status = csr_read(mstatus); in arch_user_mode_enter()
/Zephyr-Core-3.5.0/include/zephyr/arch/riscv/
Darch_inlines.h17 return csr_read(mhartid); in arch_proc_id()
23 return (_cpu_t *)csr_read(mscratch); in arch_curr_cpu()
Dcsr.h185 #define csr_read(csr) \ macro
/Zephyr-Core-3.5.0/tests/arch/riscv/fpu_sharing/src/
Dmain.c16 return csr_read(mstatus) & MSTATUS_FS; in fpu_state()
285 zassert_true((csr_read(mstatus) & MSTATUS_IEN) == 0, "IRQs should be disabled"); in exception_context()
297 zassert_true((csr_read(mstatus) & MSTATUS_IEN) != 0, "IRQs should be enabled"); in ZTEST()
301 zassert_true((csr_read(mstatus) & MSTATUS_IEN) != 0, "IRQs should be enabled"); in ZTEST()
314 zassert_true((csr_read(mstatus) & MSTATUS_IEN) != 0, "IRQs should be enabled"); in ZTEST()
325 zassert_true((csr_read(mstatus) & MSTATUS_IEN) != 0, "IRQs should be enabled"); in ZTEST()
/Zephyr-Core-3.5.0/soc/riscv/riscv-ite/common/
Dsoc_common_irq.c35 return ((csr_read(mie) & BIT(IRQ_M_EXT)) && in arch_irq_is_enabled()
/Zephyr-Core-3.5.0/soc/riscv/riscv-privileged/andes_v5/
Dpma.c98 pmacfg = csr_read(NDS_PMACFG##x); break; in write_pmacfg_entry()
206 mmsc_cfg = csr_read(NDS_MMSC_CFG); in pma_init()
Dl2_cache.c60 if (csr_read(NDS_MCACHE_CTL) & BIT_MASK(2)) { in andes_v5_l2c_enable()
/Zephyr-Core-3.5.0/soc/riscv/riscv-privileged/common/
Dsoc_common_irq.c96 mie = csr_read(mie); in arch_irq_is_enabled()
/Zephyr-Core-3.5.0/arch/riscv/include/
Dkernel_arch_func.h36 _kernel.cpus[0].arch.hartid = csr_read(mhartid); in arch_kernel_init()
/Zephyr-Core-3.5.0/drivers/interrupt_controller/
Dintc_nuclei_eclic.c176 csr_write(mtvec, ((csr_read(mtvec) & 0xFFFFFFC0) | ECLIC_MODE_MTVEC_Msk)); in nuclei_eclic_init()
Dintc_ite_it8xxx2_v2.c220 LOG_DBG("CPU mepc: 0x%lx", csr_read(mepc)); in get_irq()
Dintc_ite_it8xxx2.c233 LOG_DBG("CPU mepc: 0x%lx", csr_read(mepc)); in get_irq()
/Zephyr-Core-3.5.0/doc/releases/
Drelease-notes-3.4.rst367 * Switched from accessing CSRs from inline assembly to using the :c:func:`csr_read` helper