Searched refs:SCG_CLOCK_DIV (Results 1 – 2 of 2) sorted by relevance
| /Zephyr-latest/soc/nxp/kinetis/ke1xf/ |
| D | soc.c | 31 #define SCG_CLOCK_DIV(name) DT_PROP(SCG_CLOCK_NODE(name), clock_div) macro
35 ASSERT_WITHIN_RANGE(SCG_CLOCK_DIV(slow_clk), 2, 8,
37 ASSERT_WITHIN_RANGE(SCG_CLOCK_DIV(bus_clk), 1, 16,
41 ASSERT_WITHIN_RANGE(SCG_CLOCK_DIV(core_clk), 1, 4,
44 ASSERT_WITHIN_RANGE(SCG_CLOCK_DIV(core_clk), 1, 16,
48 .divSlow = TO_SYS_CLK_DIV(SCG_CLOCK_DIV(slow_clk)),
49 .divBus = TO_SYS_CLK_DIV(SCG_CLOCK_DIV(bus_clk)),
50 .divCore = TO_SYS_CLK_DIV(SCG_CLOCK_DIV(core_clk)),
66 ASSERT_ASYNC_CLK_DIV_VALID(SCG_CLOCK_DIV(soscdiv1_clk),
68 ASSERT_ASYNC_CLK_DIV_VALID(SCG_CLOCK_DIV(soscdiv2_clk),
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| /Zephyr-latest/soc/nxp/kinetis/ke1xz/ |
| D | soc.c | 31 #define SCG_CLOCK_DIV(name) DT_PROP(SCG_CLOCK_NODE(name), clock_div) macro
34 ASSERT_WITHIN_RANGE(SCG_CLOCK_DIV(bus_clk), 2, 8,
36 ASSERT_WITHIN_RANGE(SCG_CLOCK_DIV(core_clk), 1, 16,
40 .divSlow = TO_SYS_CLK_DIV(SCG_CLOCK_DIV(bus_clk)),
41 .divCore = TO_SYS_CLK_DIV(SCG_CLOCK_DIV(core_clk)),
50 ASSERT_ASYNC_CLK_DIV_VALID(SCG_CLOCK_DIV(sircdiv2_clk),
54 .div2 = TO_ASYNC_CLK_DIV(SCG_CLOCK_DIV(sircdiv2_clk)),
65 ASSERT_ASYNC_CLK_DIV_VALID(SCG_CLOCK_DIV(fircdiv2_clk),
69 .div2 = TO_ASYNC_CLK_DIV(SCG_CLOCK_DIV(fircdiv2_clk)), /* b20253 */
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