Lines Matching refs:SCG_CLOCK_DIV

31 #define SCG_CLOCK_DIV(name) DT_PROP(SCG_CLOCK_NODE(name), clock_div)  macro
35 ASSERT_WITHIN_RANGE(SCG_CLOCK_DIV(slow_clk), 2, 8,
37 ASSERT_WITHIN_RANGE(SCG_CLOCK_DIV(bus_clk), 1, 16,
41 ASSERT_WITHIN_RANGE(SCG_CLOCK_DIV(core_clk), 1, 4,
44 ASSERT_WITHIN_RANGE(SCG_CLOCK_DIV(core_clk), 1, 16,
48 	.divSlow = TO_SYS_CLK_DIV(SCG_CLOCK_DIV(slow_clk)),
49 	.divBus  = TO_SYS_CLK_DIV(SCG_CLOCK_DIV(bus_clk)),
50 	.divCore = TO_SYS_CLK_DIV(SCG_CLOCK_DIV(core_clk)),
66 ASSERT_ASYNC_CLK_DIV_VALID(SCG_CLOCK_DIV(soscdiv1_clk),
68 ASSERT_ASYNC_CLK_DIV_VALID(SCG_CLOCK_DIV(soscdiv2_clk),
74 	.div1        = TO_ASYNC_CLK_DIV(SCG_CLOCK_DIV(soscdiv1_clk)),
75 	.div2        = TO_ASYNC_CLK_DIV(SCG_CLOCK_DIV(soscdiv2_clk)),
81 ASSERT_ASYNC_CLK_DIV_VALID(SCG_CLOCK_DIV(sircdiv1_clk),
83 ASSERT_ASYNC_CLK_DIV_VALID(SCG_CLOCK_DIV(sircdiv2_clk),
87 	.div1       = TO_ASYNC_CLK_DIV(SCG_CLOCK_DIV(sircdiv1_clk)),
88 	.div2       = TO_ASYNC_CLK_DIV(SCG_CLOCK_DIV(sircdiv2_clk)),
99 ASSERT_ASYNC_CLK_DIV_VALID(SCG_CLOCK_DIV(fircdiv1_clk),
101 ASSERT_ASYNC_CLK_DIV_VALID(SCG_CLOCK_DIV(fircdiv2_clk),
105 	.div1       = TO_ASYNC_CLK_DIV(SCG_CLOCK_DIV(fircdiv1_clk)),
106 	.div2       = TO_ASYNC_CLK_DIV(SCG_CLOCK_DIV(fircdiv2_clk)),
122 ASSERT_WITHIN_RANGE(SCG_CLOCK_DIV(spll_clk), 2, 2,
124 ASSERT_ASYNC_CLK_DIV_VALID(SCG_CLOCK_DIV(splldiv1_clk),
126 ASSERT_ASYNC_CLK_DIV_VALID(SCG_CLOCK_DIV(splldiv2_clk),
128 ASSERT_WITHIN_RANGE(SCG_CLOCK_DIV(pll), 1, 8,
135 	.div1        = TO_ASYNC_CLK_DIV(SCG_CLOCK_DIV(splldiv1_clk)),
136 	.div2        = TO_ASYNC_CLK_DIV(SCG_CLOCK_DIV(splldiv2_clk)),
144 	.prediv      = (SCG_CLOCK_DIV(pll) - 1U),