GD32_RESET_TIMER9 (reference) in projects: Zephyr-Core-3.5.0

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Searched refs:GD32_RESET_TIMER9 (Results 1 – 8 of 8) sorted by relevance

/Zephyr-Core-3.5.0/include/zephyr/dt-bindings/reset/
D	gd32e10x.h	`43 #define GD32_RESET_TIMER9 GD32_RESET_CONFIG(APB2RST, 20U) macro`
D	gd32f403.h	`46 #define GD32_RESET_TIMER9 GD32_RESET_CONFIG(APB2RST, 20U) macro`
D	gd32e50x.h	`46 #define GD32_RESET_TIMER9 GD32_RESET_CONFIG(APB2RST, 20U) macro`
D	gd32f4xx.h	`103 #define GD32_RESET_TIMER9 GD32_RESET_CONFIG(APB2RST, 17U) macro`
/Zephyr-Core-3.5.0/dts/arm/gigadevice/gd32e50x/
D	gd32e507xe.dtsi	`53 resets = <&rctl GD32_RESET_TIMER9>;`
/Zephyr-Core-3.5.0/dts/arm/gigadevice/gd32e10x/
D	gd32e10x.dtsi	`389 resets = <&rctl GD32_RESET_TIMER9>;`
/Zephyr-Core-3.5.0/dts/arm/gigadevice/gd32f403/
D	gd32f403.dtsi	`414 resets = <&rctl GD32_RESET_TIMER9>;`
/Zephyr-Core-3.5.0/dts/arm/gigadevice/gd32f4xx/
D	gd32f4xx.dtsi	`542 resets = <&rctl GD32_RESET_TIMER9>;`

TraceRecorderSource-2.7.6
TraceRecorderSource-3.4.0
Zephyr-Core-2.7.6
Zephyr-Core-3.4.0
Zephyr-Core-3.5.0
Zephyr-Core-3.6.0
Zephyr-Core-3.7.0
acpica-3.5.0
acpica-3.6.0
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babblesim_ext_2G4_channel_multiatt-3.4.0
babblesim_ext_2G4_channel_multiatt-3.7.0-3.6.0-3.5.0
babblesim_ext_2G4_device_WLAN_actmod-3.7.0-3.6.0-3.5.0-3.4.0
babblesim_ext_2G4_device_burst_interferer-3.7.0-3.6.0-3.5.0-3.4.0
babblesim_ext_2G4_device_playback-3.6.0-3.5.0-3.4.0
babblesim_ext_2G4_device_playback-3.7.0
babblesim_ext_2G4_libPhyComv1-3.6.0-3.5.0-3.4.0
babblesim_ext_2G4_libPhyComv1-3.7.0
babblesim_ext_2G4_modem_BLE_simple-3.4.0
babblesim_ext_2G4_modem_BLE_simple-3.6.0-3.5.0
babblesim_ext_2G4_modem_BLE_simple-3.7.0
babblesim_ext_2G4_modem_magic-3.6.0-3.5.0-3.4.0
babblesim_ext_2G4_modem_magic-3.7.0
babblesim_ext_2G4_phy_v1-3.4.0
babblesim_ext_2G4_phy_v1-3.6.0-3.5.0
babblesim_ext_2G4_phy_v1-3.7.0
babblesim_ext_libCryptov1-3.7.0-3.6.0-3.5.0-3.4.0
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