Home
last modified time | relevance | path

Searched refs:CPG_MOD (Results 1 – 7 of 7) sorted by relevance

/Zephyr-Core-3.5.0/dts/arm/renesas/rcar/gen3/
Dr8a77951.dtsi19 clocks = <&cpg CPG_MOD 916>,
24 clocks = <&cpg CPG_MOD 523>,
29 clocks = <&cpg CPG_MOD 206>,
34 clocks = <&cpg CPG_MOD 310>,
Drcar_gen3_cr7.dtsi51 clocks = <&cpg CPG_MOD 907>;
62 clocks = <&cpg CPG_MOD 906>;
87 clocks = <&cpg CPG_MOD 303>;
110 clocks = <&cpg CPG_MOD 929>;
123 clocks = <&cpg CPG_MOD 927>;
/Zephyr-Core-3.5.0/include/zephyr/dt-bindings/clock/
Drenesas_cpg_mssr.h11 #define CPG_MOD 1 /* Module Clock */ macro
/Zephyr-Core-3.5.0/dts/arm64/renesas/
Drcar_gen3_ca57.dtsi61 clocks = <&cpg CPG_MOD 312>;
75 clocks = <&cpg CPG_MOD 310>,
/Zephyr-Core-3.5.0/drivers/clock_control/
Dclock_control_r8a7795_cpg_mssr.c160 if (clk->domain == CPG_MOD) { in r8a7795_cpg_mssr_start_stop()
297 .cmn.clk_info_table[CPG_MOD] = mod_props, \
298 .cmn.clk_info_table_size[CPG_MOD] = ARRAY_SIZE(mod_props), \
Dclock_control_renesas_cpg_mssr.h66 .domain = CPG_MOD, \
Dclock_control_renesas_cpg_mssr.c97 if (clk_info->domain == CPG_MOD) { in rcar_cpg_get_divider()
283 if (clk_info->domain == CPG_MOD) { in rcar_cpg_set_rate()