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Searched refs:t0 (Results 1 – 25 of 42) sorted by relevance

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/Zephyr-Core-3.4.0/soc/riscv/riscv-privileged/andes_v5/
Dstart.S20 la t0, _ITB_BASE_
21 csrw uitb, t0
30 li t0, (0x3 << 13)
31 csrc NDS_MCACHE_CTL, t0
32 li t0, (1 << 19) | (1 << 13) | (1 << 10) | (1 << 9) | (0x3)
33 csrs NDS_MCACHE_CTL, t0
36 csrr t0, NDS_MCACHE_CTL
38 and t0, t0, t1
39 beqz t0, cache_enable_finish
44 csrr t0, NDS_MCACHE_CTL
[all …]
Dsoc_irq.S21 csrr t0, NDS_MXSTATUS
28 sw t0, __soc_esf_t_mxstatus_OFFSET(a0)
38 lw t0, __soc_esf_t_mxstatus_OFFSET(a0)
45 csrw NDS_MXSTATUS, t0
/Zephyr-Core-3.4.0/arch/riscv/core/
Dreset.S42 li t0, CONFIG_RV_BOOT_HART
43 beq a0, t0, boot_first_core
52 li t0, MSTATUS_FS_INIT
53 csrs mstatus, t0
64 la t0, z_interrupt_stacks
66 add t1, t1, t0
71 sw t2, 0x00(t0)
72 addi t0, t0, 4
73 blt t0, t1, aa_loop
81 li t0, __z_interrupt_stack_SIZEOF
[all …]
Disr.S26 RV_E( op t0, __z_arch_esf_t_t0_OFFSET(sp) );\
111 sr t0, _curr_cpu_arch_user_exc_tmp0(s0)
115 csrr t0, mstatus
117 and t0, t0, t1
118 bnez t0, 1f
121 mv t0, sp
127 sr t0, (-__z_arch_esf_t_SIZEOF + __z_arch_esf_t_sp_OFFSET)(sp)
130 lr t0, ___cpu_t_current_OFFSET(s0)
131 lr tp, _thread_offset_to_tls(t0)
134 lui t0, %tprel_hi(is_user_mode)
[all …]
Dpmp.S39 la t0, pmpaddr_store
41 add t0, t0, t1
42 jr t0
50 lr t0, (RV_REGSIZE * _index)(a3)
52 csrw (CSR_PMPADDR_BASE + _index), t0
65 la t0, pmpcfg_store
68 add t0, t0, t1
71 jr t0
79 lr t0, (RV_REGSIZE * _index)(a4)
81 csrw (CSR_PMPCFG_BASE + RV_REGSIZE/4 * _index), t0
[all …]
Dswitch.S75 lb t0, _thread_offset_to_user_options(a0)
76 andi t0, t0, K_USER
77 beqz t0, not_user_task
Dfpu.S57 frcsr t0
59 sw t0, __z_riscv_fp_context_t_fcsr_OFFSET(a0)
66 lw t0, __z_riscv_fp_context_t_fcsr_OFFSET(a0)
67 fscsr t0
Dcoredump.c16 uint32_t t0; member
64 arch_blk.r.t0 = esf->t0; in arch_coredump_info_dump()
/Zephyr-Core-3.4.0/soc/riscv/riscv-privileged/telink_b91/
Dstart.S35 csrr t0, NDS_MCACHE_CTL
36 ori t0, t0, 1 #/I-Cache
37 ori t0, t0, 2 #/D-Cache
38 csrw NDS_MCACHE_CTL, t0
42 li t0, (1 << 8) | (1 << 6)
43 csrs NDS_MMISC_CTL, t0
46 lui t0, 0
51 sw t0, 0(t2)
61 lw t0, 0(t1)
62 sw t0, 0(t2)
[all …]
Dsoc_irq.S25 csrr t0, NDS_MXSTATUS
32 sw t0, __soc_esf_t_mxstatus_OFFSET(a0)
42 lw t0, __soc_esf_t_mxstatus_OFFSET(a0)
49 csrw NDS_MXSTATUS, t0
/Zephyr-Core-3.4.0/soc/riscv/openisa_rv32m1/
Dsoc_irq.S43 la t0, __EVENT_INTPTPENDCLEAR
46 sw t1, 0x00(t0)
62 csrr t0, RI5CY_LPSTART0
65 sw t0, __soc_esf_t_lpstart0_OFFSET(a0)
68 csrr t0, RI5CY_LPSTART1
71 sw t0, __soc_esf_t_lpstart1_OFFSET(a0)
80 lw t0, __soc_esf_t_lpstart0_OFFSET(a0)
83 csrw RI5CY_LPSTART0, t0
86 lw t0, __soc_esf_t_lpstart1_OFFSET(a0)
89 csrw RI5CY_LPSTART1, t0
Dwdog.S42 csrrc t0, mstatus, MSTATUS_IEN
62 csrrs x0, mstatus, t0
Dvector.S77 la t0, ivt
78 csrw 0x305, t0
/Zephyr-Core-3.4.0/include/zephyr/arch/riscv/
Dsyscall.h50 register unsigned long t0 __asm__ ("t0") = call_id; in arch_syscall_invoke6()
55 "r" (t0) in arch_syscall_invoke6()
70 register unsigned long t0 __asm__ ("t0") = call_id; in arch_syscall_invoke5()
74 : "r" (a1), "r" (a2), "r" (a3), "r" (a4), "r" (t0) in arch_syscall_invoke5()
87 register unsigned long t0 __asm__ ("t0") = call_id; in arch_syscall_invoke4()
91 : "r" (a1), "r" (a2), "r" (a3), "r" (t0) in arch_syscall_invoke4()
103 register unsigned long t0 __asm__ ("t0") = call_id; in arch_syscall_invoke3()
107 : "r" (a1), "r" (a2), "r" (t0) in arch_syscall_invoke3()
117 register unsigned long t0 __asm__ ("t0") = call_id; in arch_syscall_invoke2()
121 : "r" (a1), "r" (t0) in arch_syscall_invoke2()
[all …]
/Zephyr-Core-3.4.0/soc/riscv/riscv-privileged/common/
Dsoc_irq.S30 sll t0, t1, a0
31 csrrc t1, mip, t0
50 csrr t0, mcause
52 and t0, t0, t1
56 beqz t0, not_interrupt
Dvector.S39 la t0, _irq_vector_table /* Load address of interrupt vector table */
40 addi t0, t0, 1 /* Enable vectored mode by setting LSB */
48 la t0, _isr_wrapper
51 csrw mtvec, t0
/Zephyr-Core-3.4.0/arch/mips/core/
Dreset.S34 la t0, z_interrupt_stacks
36 add t1, t1, t0
41 sw t2, 0(t0)
42 addi t0, t0, 4
43 blt t0, t1, aa_loop
Disr.S43 op t0, ESF_O(t0)(sp) ;\
89 mfhi t0
91 OP_STOREREG t0, ESF_O(hi)(sp)
93 mfc0 t0, CP0_EPC
94 OP_STOREREG t0, ESF_O(epc)(sp)
97 mfc0 t0, CP0_STATUS
98 OP_STOREREG t0, ESF_O(status)(sp)
114 and t1, t1, t0
148 la t0, _offload_routine
149 OP_LOADREG t1, 0(t0)
[all …]
/Zephyr-Core-3.4.0/soc/riscv/riscv-ite/common/
Dvector.S33 la t0, _isr_wrapper
34 csrw mtvec, t0
41 la t0, IT8XXX2_GCTRL_EIDSR
42 lb t1, 0(t0)
45 sb t1, 0(t0)
/Zephyr-Core-3.4.0/tests/kernel/tickless/tickless_concept/src/
Dmain.c71 volatile uint32_t t0, t1; in ZTEST() local
74 t0 = k_uptime_get_32(); in ZTEST()
77 TC_PRINT("time %d, %d\n", t0, t1); in ZTEST()
79 zassert_true((t1 - t0) >= SLEEP_TICKLESS); in ZTEST()
82 t0 = k_uptime_get_32(); in ZTEST()
85 TC_PRINT("time %d, %d\n", t0, t1); in ZTEST()
87 zassert_true((t1 - t0) >= SLEEP_TICKFUL); in ZTEST()
/Zephyr-Core-3.4.0/soc/riscv/riscv-privileged/neorv32/
Dsoc_irq.S22 sll t0, t1, a0
23 csrrc t2, mie, t0
24 and t1, t2, t0
/Zephyr-Core-3.4.0/soc/riscv/riscv-privileged/gd32vf103/
Dentry.S39 li t0, 0x200
40 csrs CSR_MMISC_CTL, t0
43 la t0, trap_entry
44 csrw mtvec, t0
/Zephyr-Core-3.4.0/tests/subsys/fs/littlefs/src/
Dtest_lfs_perf.c33 uint32_t t0; in write_read() local
87 t0 = k_uptime_get_32(); in write_read()
97 if (t1 == t0) { in write_read()
116 tag, nbuf, buf_size, total, (t1 - t0), in write_read()
117 (uint32_t)(total * 1000U / (t1 - t0)), in write_read()
118 (uint32_t)(total * 1000U / (t1 - t0) / 1024U)); in write_read()
126 t0 = k_uptime_get_32(); in write_read()
136 if (t1 == t0) { in write_read()
142 tag, nbuf, buf_size, total, (t1 - t0), in write_read()
143 (uint32_t)(total * 1000U / (t1 - t0)), in write_read()
[all …]
/Zephyr-Core-3.4.0/tests/subsys/logging/log_cache/src/
Dmain.c37 union test_ids t0 = { .raw = id0 }; in cmp() local
40 return (t0.id.x == t1.id.x) && (t0.id.y == t1.id.y); in cmp()
/Zephyr-Core-3.4.0/include/zephyr/arch/mips/
Dexp.h24 unsigned long t0; /* Caller-saved temporary register */ member

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