| /Zephyr-Core-3.4.0/tests/kernel/fpu_sharing/generic/src/ |
| D | float_regs_xtensa.h | 29 static inline void _load_all_float_registers(struct fp_register_set *regs) in _load_all_float_registers() argument
31 __asm__ volatile("wfr f0, %0\n" :: "r"(regs->fp_non_volatile.reg[0])); in _load_all_float_registers()
32 __asm__ volatile("wfr f1, %0\n" :: "r"(regs->fp_non_volatile.reg[1])); in _load_all_float_registers()
33 __asm__ volatile("wfr f2, %0\n" :: "r"(regs->fp_non_volatile.reg[2])); in _load_all_float_registers()
34 __asm__ volatile("wfr f3, %0\n" :: "r"(regs->fp_non_volatile.reg[3])); in _load_all_float_registers()
35 __asm__ volatile("wfr f4, %0\n" :: "r"(regs->fp_non_volatile.reg[4])); in _load_all_float_registers()
36 __asm__ volatile("wfr f5, %0\n" :: "r"(regs->fp_non_volatile.reg[5])); in _load_all_float_registers()
37 __asm__ volatile("wfr f6, %0\n" :: "r"(regs->fp_non_volatile.reg[6])); in _load_all_float_registers()
38 __asm__ volatile("wfr f7, %0\n" :: "r"(regs->fp_non_volatile.reg[7])); in _load_all_float_registers()
39 __asm__ volatile("wfr f8, %0\n" :: "r"(regs->fp_non_volatile.reg[8])); in _load_all_float_registers()
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| D | float_regs_arm_gcc.h | 40 static inline void _load_all_float_registers(struct fp_register_set *regs) in _load_all_float_registers() argument
45 : : "r" (®s->fp_volatile), "r" (®s->fp_non_volatile) in _load_all_float_registers()
60 static inline void _store_all_float_registers(struct fp_register_set *regs) in _store_all_float_registers() argument
65 : : "r" (®s->fp_volatile), "r" (®s->fp_non_volatile) in _store_all_float_registers()
84 *regs) in _load_then_store_all_float_registers()
86 _load_all_float_registers(regs); in _load_then_store_all_float_registers()
87 _store_all_float_registers(regs); in _load_then_store_all_float_registers()
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| /Zephyr-Core-3.4.0/drivers/display/ |
| D | display_ili9341.c | 18 const struct ili9341_regs *regs = config->regs; in ili9341_regs_init() local
22 LOG_HEXDUMP_DBG(regs->pwseqctrl, ILI9341_PWSEQCTRL_LEN, "PWSEQCTRL"); in ili9341_regs_init()
23 r = ili9xxx_transmit(dev, ILI9341_PWSEQCTRL, regs->pwseqctrl, ILI9341_PWSEQCTRL_LEN); in ili9341_regs_init()
28 LOG_HEXDUMP_DBG(regs->timctrla, ILI9341_TIMCTRLA_LEN, "TIMCTRLA"); in ili9341_regs_init()
29 r = ili9xxx_transmit(dev, ILI9341_TIMCTRLA, regs->timctrla, ILI9341_TIMCTRLA_LEN); in ili9341_regs_init()
34 LOG_HEXDUMP_DBG(regs->timctrlb, ILI9341_TIMCTRLB_LEN, "TIMCTRLB"); in ili9341_regs_init()
35 r = ili9xxx_transmit(dev, ILI9341_TIMCTRLB, regs->timctrlb, ILI9341_TIMCTRLB_LEN); in ili9341_regs_init()
40 LOG_HEXDUMP_DBG(regs->pumpratioctrl, ILI9341_PUMPRATIOCTRL_LEN, "PUMPRATIOCTRL"); in ili9341_regs_init()
41 r = ili9xxx_transmit(dev, ILI9341_PUMPRATIOCTRL, regs->pumpratioctrl, in ili9341_regs_init()
47 LOG_HEXDUMP_DBG(regs->pwctrla, ILI9341_PWCTRLA_LEN, "PWCTRLA"); in ili9341_regs_init()
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| D | display_ili9342c.c | 19 const struct ili9342c_regs *regs = config->regs; in ili9342c_regs_init() local
23 LOG_HEXDUMP_DBG(regs->setextc, ILI9342C_SETEXTC_LEN, "SETEXTC"); in ili9342c_regs_init()
24 r = ili9xxx_transmit(dev, ILI9342C_SETEXTC, regs->setextc, in ili9342c_regs_init()
30 LOG_HEXDUMP_DBG(regs->gamset, ILI9342C_GAMSET_LEN, "GAMSET"); in ili9342c_regs_init()
31 r = ili9xxx_transmit(dev, ILI9342C_GAMSET, regs->gamset, in ili9342c_regs_init()
37 LOG_HEXDUMP_DBG(regs->ifmode, ILI9342C_IFMODE_LEN, "IFMODE"); in ili9342c_regs_init()
38 r = ili9xxx_transmit(dev, ILI9342C_IFMODE, regs->ifmode, in ili9342c_regs_init()
44 LOG_HEXDUMP_DBG(regs->frmctr1, ILI9342C_FRMCTR1_LEN, "FRMCTR1"); in ili9342c_regs_init()
45 r = ili9xxx_transmit(dev, ILI9342C_FRMCTR1, regs->frmctr1, in ili9342c_regs_init()
51 LOG_HEXDUMP_DBG(regs->invtr, ILI9342C_INVTR_LEN, "INVTR"); in ili9342c_regs_init()
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| D | display_ili9340.c | 16 const struct ili9340_regs *regs = config->regs; in ili9340_regs_init() local
20 LOG_HEXDUMP_DBG(regs->gamset, ILI9340_GAMSET_LEN, "GAMSET"); in ili9340_regs_init()
21 r = ili9xxx_transmit(dev, ILI9340_GAMSET, regs->gamset, in ili9340_regs_init()
27 LOG_HEXDUMP_DBG(regs->frmctr1, ILI9340_FRMCTR1_LEN, "FRMCTR1"); in ili9340_regs_init()
28 r = ili9xxx_transmit(dev, ILI9340_FRMCTR1, regs->frmctr1, in ili9340_regs_init()
34 LOG_HEXDUMP_DBG(regs->disctrl, ILI9340_DISCTRL_LEN, "DISCTRL"); in ili9340_regs_init()
35 r = ili9xxx_transmit(dev, ILI9340_DISCTRL, regs->disctrl, in ili9340_regs_init()
41 LOG_HEXDUMP_DBG(regs->pwctrl1, ILI9340_PWCTRL1_LEN, "PWCTRL1"); in ili9340_regs_init()
42 r = ili9xxx_transmit(dev, ILI9340_PWCTRL1, regs->pwctrl1, in ili9340_regs_init()
48 LOG_HEXDUMP_DBG(regs->pwctrl2, ILI9340_PWCTRL2_LEN, "PWCTRL2"); in ili9340_regs_init()
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| D | display_ili9488.c | 16 const struct ili9488_regs *regs = config->regs; in ili9488_regs_init() local
20 LOG_HEXDUMP_DBG(regs->frmctr1, ILI9488_FRMCTR1_LEN, "FRMCTR1"); in ili9488_regs_init()
21 r = ili9xxx_transmit(dev, ILI9488_FRMCTR1, regs->frmctr1, in ili9488_regs_init()
27 LOG_HEXDUMP_DBG(regs->disctrl, ILI9488_DISCTRL_LEN, "DISCTRL"); in ili9488_regs_init()
28 r = ili9xxx_transmit(dev, ILI9488_DISCTRL, regs->disctrl, in ili9488_regs_init()
34 LOG_HEXDUMP_DBG(regs->pwctrl1, ILI9488_PWCTRL1_LEN, "PWCTRL1"); in ili9488_regs_init()
35 r = ili9xxx_transmit(dev, ILI9488_PWCTRL1, regs->pwctrl1, in ili9488_regs_init()
41 LOG_HEXDUMP_DBG(regs->pwctrl2, ILI9488_PWCTRL2_LEN, "PWCTRL2"); in ili9488_regs_init()
42 r = ili9xxx_transmit(dev, ILI9488_PWCTRL2, regs->pwctrl2, in ili9488_regs_init()
48 LOG_HEXDUMP_DBG(regs->vmctrl, ILI9488_VMCTRL_LEN, "VMCTRL"); in ili9488_regs_init()
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| /Zephyr-Core-3.4.0/drivers/serial/ |
| D | uart_apbuart.c | 127 struct apbuart_regs *regs; member
147 volatile struct apbuart_regs *regs = (void *) config->regs; in apbuart_poll_out() local
151 while (regs->status & APBUART_STATUS_TF) { in apbuart_poll_out()
159 while (!(regs->status & APBUART_STATUS_HOLD_REGISTER_EMPTY)) { in apbuart_poll_out()
164 regs->data = x & 0xff; in apbuart_poll_out()
170 volatile struct apbuart_regs *regs = (void *) config->regs; in apbuart_poll_in() local
172 if ((regs->status & APBUART_STATUS_DR) == 0) { in apbuart_poll_in()
175 *c = regs->data & 0xff; in apbuart_poll_in()
183 volatile struct apbuart_regs *regs = (void *) config->regs; in apbuart_err_check() local
184 const uint32_t status = regs->status; in apbuart_err_check()
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| /Zephyr-Core-3.4.0/drivers/espi/ |
| D | espi_saf_mchp_xec.c | 72 static inline void mchp_saf_cs_descr_wr(MCHP_SAF_HW_REGS *regs, uint8_t cs, in mchp_saf_cs_descr_wr() argument
75 regs->SAF_CS_OP[cs].OP_DESCR = val; in mchp_saf_cs_descr_wr()
78 static inline void mchp_saf_poll2_mask_wr(MCHP_SAF_HW_REGS *regs, uint8_t cs, in mchp_saf_poll2_mask_wr() argument
83 regs->SAF_CS0_CFG_P2M = val; in mchp_saf_poll2_mask_wr()
85 regs->SAF_CS1_CFG_P2M = val; in mchp_saf_poll2_mask_wr()
89 static inline void mchp_saf_cm_prefix_wr(MCHP_SAF_HW_REGS *regs, uint8_t cs, in mchp_saf_cm_prefix_wr() argument
93 regs->SAF_CS0_CM_PRF = val; in mchp_saf_cm_prefix_wr()
95 regs->SAF_CS1_CM_PRF = val; in mchp_saf_cm_prefix_wr()
145 static void saf_protection_regions_init(MCHP_SAF_HW_REGS *regs) in saf_protection_regions_init() argument
151 regs->SAF_PROT_RG[0].START = 0U; in saf_protection_regions_init()
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| D | espi_saf_mchp_xec_v2.c | 96 static inline void mchp_saf_cs_descr_wr(struct mchp_espi_saf *regs, uint8_t cs, in mchp_saf_cs_descr_wr() argument
99 regs->SAF_CS_OP[cs].OP_DESCR = val; in mchp_saf_cs_descr_wr()
102 static inline void mchp_saf_poll2_mask_wr(struct mchp_espi_saf *regs, uint8_t cs, in mchp_saf_poll2_mask_wr() argument
107 regs->SAF_CS0_CFG_P2M = val; in mchp_saf_poll2_mask_wr()
109 regs->SAF_CS1_CFG_P2M = val; in mchp_saf_poll2_mask_wr()
113 static inline void mchp_saf_cm_prefix_wr(struct mchp_espi_saf *regs, uint8_t cs, in mchp_saf_cm_prefix_wr() argument
117 regs->SAF_CS0_CM_PRF = val; in mchp_saf_cm_prefix_wr()
119 regs->SAF_CS1_CM_PRF = val; in mchp_saf_cm_prefix_wr()
151 static void saf_protection_regions_init(struct mchp_espi_saf *regs) in saf_protection_regions_init() argument
157 regs->SAF_PROT_RG[0].START = 0U; in saf_protection_regions_init()
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| /Zephyr-Core-3.4.0/drivers/flash/ |
| D | flash_stm32l4x.c | 43 static inline void flush_cache(FLASH_TypeDef *regs) in flush_cache() argument
45 if (regs->ACR & FLASH_ACR_DCEN) { in flush_cache()
46 regs->ACR &= ~FLASH_ACR_DCEN; in flush_cache()
50 regs->ACR |= FLASH_ACR_DCRST; in flush_cache()
51 regs->ACR &= ~FLASH_ACR_DCRST; in flush_cache()
52 regs->ACR |= FLASH_ACR_DCEN; in flush_cache()
55 if (regs->ACR & FLASH_ACR_ICEN) { in flush_cache()
56 regs->ACR &= ~FLASH_ACR_ICEN; in flush_cache()
61 regs->ACR |= FLASH_ACR_ICRST; in flush_cache()
62 regs->ACR &= ~FLASH_ACR_ICRST; in flush_cache()
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| D | flash_stm32f1x.c | 46 static int is_flash_locked(FLASH_TypeDef *regs) in is_flash_locked() argument
48 return !!(regs->CR & FLASH_CR_LOCK); in is_flash_locked()
51 static void write_enable(FLASH_TypeDef *regs) in write_enable() argument
53 regs->CR |= FLASH_CR_PG; in write_enable()
56 static void write_disable(FLASH_TypeDef *regs) in write_disable() argument
58 regs->CR &= (~FLASH_CR_PG); in write_disable()
61 static void erase_page_begin(FLASH_TypeDef *regs, unsigned int page) in erase_page_begin() argument
64 regs->CR |= FLASH_CR_PER; in erase_page_begin()
65 regs->AR = CONFIG_FLASH_BASE_ADDRESS + page * FLASH_PAGE_SIZE; in erase_page_begin()
70 regs->CR |= FLASH_CR_STRT; in erase_page_begin()
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| D | flash_stm32g4x.c | 49 static inline void flush_cache(FLASH_TypeDef *regs) in flush_cache() argument
51 if (regs->ACR & FLASH_ACR_DCEN) { in flush_cache()
52 regs->ACR &= ~FLASH_ACR_DCEN; in flush_cache()
56 regs->ACR |= FLASH_ACR_DCRST; in flush_cache()
57 regs->ACR &= ~FLASH_ACR_DCRST; in flush_cache()
58 regs->ACR |= FLASH_ACR_DCEN; in flush_cache()
61 if (regs->ACR & FLASH_ACR_ICEN) { in flush_cache()
62 regs->ACR &= ~FLASH_ACR_ICEN; in flush_cache()
67 regs->ACR |= FLASH_ACR_ICRST; in flush_cache()
68 regs->ACR &= ~FLASH_ACR_ICRST; in flush_cache()
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| D | flash_stm32f2x.c | 25 static inline void flush_cache(FLASH_TypeDef *regs) in flush_cache() argument
30 if (regs->ACR & FLASH_ACR_DCEN) { in flush_cache()
31 regs->ACR &= ~FLASH_ACR_DCEN; in flush_cache()
35 regs->ACR |= FLASH_ACR_DCRST; in flush_cache()
36 regs->ACR &= ~FLASH_ACR_DCRST; in flush_cache()
37 regs->ACR |= FLASH_ACR_DCEN; in flush_cache()
43 if (regs->ACR & FLASH_ACR_ICEN) { in flush_cache()
44 regs->ACR &= ~FLASH_ACR_ICEN; in flush_cache()
49 regs->ACR |= FLASH_ACR_ICRST; in flush_cache()
50 regs->ACR &= ~FLASH_ACR_ICRST; in flush_cache()
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| D | flash_stm32f4x.c | 30 FLASH_TypeDef *regs = FLASH_STM32_REGS(dev); in flash_stm32_valid_range() local
34 if (regs->OPTCR & FLASH_OPTCR_DB1M) { in flash_stm32_valid_range()
43 static inline void flush_cache(FLASH_TypeDef *regs) in flush_cache() argument
45 if (regs->ACR & FLASH_ACR_DCEN) { in flush_cache()
46 regs->ACR &= ~FLASH_ACR_DCEN; in flush_cache()
50 regs->ACR |= FLASH_ACR_DCRST; in flush_cache()
51 regs->ACR &= ~FLASH_ACR_DCRST; in flush_cache()
52 regs->ACR |= FLASH_ACR_DCEN; in flush_cache()
55 if (regs->ACR & FLASH_ACR_ICEN) { in flush_cache()
56 regs->ACR &= ~FLASH_ACR_ICEN; in flush_cache()
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| D | flash_stm32wbx.c | 48 static inline void flush_cache(FLASH_TypeDef *regs) in flush_cache() argument
50 if (regs->ACR & FLASH_ACR_DCEN) { in flush_cache()
51 regs->ACR &= ~FLASH_ACR_DCEN; in flush_cache()
55 regs->ACR |= FLASH_ACR_DCRST; in flush_cache()
56 regs->ACR &= ~FLASH_ACR_DCRST; in flush_cache()
57 regs->ACR |= FLASH_ACR_DCEN; in flush_cache()
60 if (regs->ACR & FLASH_ACR_ICEN) { in flush_cache()
61 regs->ACR &= ~FLASH_ACR_ICEN; in flush_cache()
66 regs->ACR |= FLASH_ACR_ICRST; in flush_cache()
67 regs->ACR &= ~FLASH_ACR_ICRST; in flush_cache()
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| D | flash_stm32.c | 142 FLASH_TypeDef *regs = FLASH_STM32_REGS(dev); in flash_stm32_flush_caches()
144 if (regs->ACR & FLASH_ACR_DCEN) { in flash_stm32_flush_caches()
145 regs->ACR &= ~FLASH_ACR_DCEN; in flash_stm32_flush_caches()
146 regs->ACR |= FLASH_ACR_DCRST; in flash_stm32_flush_caches()
147 regs->ACR &= ~FLASH_ACR_DCRST; in flash_stm32_flush_caches()
148 regs->ACR |= FLASH_ACR_DCEN; in flash_stm32_flush_caches()
251 FLASH_TypeDef *regs = FLASH_STM32_REGS(dev); in flash_stm32_write_protection() local
265 regs->NSCR |= FLASH_STM32_NSLOCK; in flash_stm32_write_protection()
267 if (regs->NSCR & FLASH_STM32_NSLOCK) { in flash_stm32_write_protection()
268 regs->NSKEYR = FLASH_KEY1; in flash_stm32_write_protection()
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| /Zephyr-Core-3.4.0/drivers/spi/ |
| D | spi_xec_qmspi.c | 21 QMSPI_Type *regs; member
39 static inline uint32_t descr_rd(QMSPI_Type *regs, uint32_t did) in descr_rd() argument
41 uintptr_t raddr = (uintptr_t)regs + MCHP_QMSPI_DESC0_OFS + in descr_rd()
47 static inline void descr_wr(QMSPI_Type *regs, uint32_t did, uint32_t val) in descr_wr() argument
49 uintptr_t raddr = (uintptr_t)regs + MCHP_QMSPI_DESC0_OFS + in descr_wr()
55 static inline void txb_wr8(QMSPI_Type *regs, uint8_t data8) in txb_wr8() argument
57 REG8(®s->TX_FIFO) = data8; in txb_wr8()
60 static inline uint8_t rxb_rd8(QMSPI_Type *regs) in rxb_rd8() argument
62 return REG8(®s->RX_FIFO); in rxb_rd8()
71 static void qmspi_set_frequency(QMSPI_Type *regs, uint32_t freq_hz) in qmspi_set_frequency() argument
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| D | spi_xec_qmspi_ldma.c | 71 struct qmspi_regs *regs; member
135 static void qmspi_reset(struct qmspi_regs *regs) in qmspi_reset() argument
143 taps[0] = regs->TM_TAPS; in qmspi_reset()
144 taps[1] = regs->TM_TAPS_ADJ; in qmspi_reset()
145 taps[2] = regs->TM_TAPS_CTRL; in qmspi_reset()
146 malt1 = regs->MODE_ALT1; in qmspi_reset()
147 cstm = regs->CSTM; in qmspi_reset()
148 mode = regs->MODE; in qmspi_reset()
149 regs->MODE = MCHP_QMSPI_M_SRST; in qmspi_reset()
150 while (regs->MODE & MCHP_QMSPI_M_SRST) { in qmspi_reset()
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| /Zephyr-Core-3.4.0/drivers/watchdog/ |
| D | wdt_mchp_xec.c | 24 struct wdt_regs *regs; member
38 struct wdt_regs *regs = cfg->regs; in wdt_xec_setup() local
40 if (regs->CTRL & MCHP_WDT_CTRL_EN) { in wdt_xec_setup()
55 regs->CTRL |= MCHP_WDT_CTRL_JTAG_STALL_EN; in wdt_xec_setup()
57 regs->CTRL &= ~MCHP_WDT_CTRL_JTAG_STALL_EN; in wdt_xec_setup()
60 regs->CTRL |= MCHP_WDT_CTRL_EN; in wdt_xec_setup()
71 struct wdt_regs *regs = cfg->regs; in wdt_xec_disable() local
73 if (!(regs->CTRL & MCHP_WDT_CTRL_EN)) { in wdt_xec_disable()
77 regs->CTRL &= ~MCHP_WDT_CTRL_EN; in wdt_xec_disable()
90 struct wdt_regs *regs = cfg->regs; in wdt_xec_install_timeout() local
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| /Zephyr-Core-3.4.0/drivers/peci/ |
| D | peci_mchp_xec.c | 47 struct peci_regs * const regs; member
132 static int check_bus_idle(struct peci_regs * const regs) in check_bus_idle() argument
140 while (!(regs->STATUS2 & MCHP_PECI_STS2_IDLE)) { in check_bus_idle()
156 struct peci_regs * const regs = cfg->regs; in peci_xec_configure() local
162 regs->CONTROL = MCHP_PECI_CTRL_PD; in peci_xec_configure()
166 regs->OPT_BIT_TIME_LSB = value & MCHP_PECI_OPT_BT_LSB_MASK; in peci_xec_configure()
167 regs->OPT_BIT_TIME_MSB = ((value >> OPT_BIT_TIME_MSB_OFS) & in peci_xec_configure()
171 regs->CONTROL &= ~MCHP_PECI_CTRL_PD; in peci_xec_configure()
179 struct peci_regs * const regs = cfg->regs; in peci_xec_disable() local
183 ret = check_bus_idle(regs); in peci_xec_disable()
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| /Zephyr-Core-3.4.0/drivers/eeprom/ |
| D | eeprom_mchp_xec.c | 63 struct eeprom_xec_regs * const regs; member
72 static void eeprom_xec_execute_reg_set(struct eeprom_xec_regs * const regs, in eeprom_xec_execute_reg_set() argument
81 regs->execute = temp; in eeprom_xec_execute_reg_set()
84 static uint8_t eeprom_xec_data_buffer_read(struct eeprom_xec_regs * const regs, in eeprom_xec_data_buffer_read() argument
93 *destination_ptr = regs->buffer[count]; in eeprom_xec_data_buffer_read()
100 static uint8_t eeprom_xec_data_buffer_write(struct eeprom_xec_regs * const regs, in eeprom_xec_data_buffer_write() argument
109 regs->buffer[count] = *source_ptr; in eeprom_xec_data_buffer_write()
116 static void eeprom_xec_wait_transfer_compl(struct eeprom_xec_regs * const regs) in eeprom_xec_wait_transfer_compl() argument
130 sts = XEC_EEPROM_STS_TRANSFER_COMPL & regs->status; in eeprom_xec_wait_transfer_compl()
137 regs->status = XEC_EEPROM_STS_TRANSFER_COMPL; in eeprom_xec_wait_transfer_compl()
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| /Zephyr-Core-3.4.0/drivers/pwm/ |
| D | pwm_sam0_tcc.c | 22 Tcc *regs; member
40 static void wait_synchronization(Tcc *regs) in wait_synchronization() argument
42 while (regs->SYNCBUSY.reg != 0) { in wait_synchronization()
64 Tcc *regs = cfg->regs; in pwm_sam0_set_cycles() local
68 bool inverted = ((regs->DRVCTRL.vec.INVEN & invert_mask) != 0); in pwm_sam0_set_cycles()
83 regs->CCBUF[channel].reg = TCC_CCBUF_CCBUF(pulse_cycles); in pwm_sam0_set_cycles()
84 regs->PERBUF.reg = TCC_PERBUF_PERBUF(period_cycles); in pwm_sam0_set_cycles()
87 regs->CCB[channel].reg = TCC_CCB_CCB(pulse_cycles); in pwm_sam0_set_cycles()
88 regs->PERB.reg = TCC_PERB_PERB(period_cycles); in pwm_sam0_set_cycles()
92 regs->CTRLA.bit.ENABLE = 0; in pwm_sam0_set_cycles()
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| /Zephyr-Core-3.4.0/drivers/usb/device/ |
| D | usb_dc_sam_usbc.c | 104 static volatile Usbc *regs = (Usbc *) DT_INST_REG_ADDR(0); variable
122 if (regs->UESTA[ep_idx] != dev_ep_sta_dbg[0][ep_idx]) { in usb_dc_sam_usbc_isr_sta_dbg()
123 dev_ep_sta_dbg[0][ep_idx] = regs->UESTA[ep_idx]; in usb_dc_sam_usbc_isr_sta_dbg()
128 regs->UDCON, regs->UDINT, regs->UDINTE, in usb_dc_sam_usbc_isr_sta_dbg()
129 regs->UECON[ep_idx], regs->UESTA[ep_idx], in usb_dc_sam_usbc_isr_sta_dbg()
136 regs->UDCON, regs->UDINT, regs->UDINTE, in usb_dc_sam_usbc_isr_sta_dbg()
137 regs->UECON[ep_idx], regs->UESTA[ep_idx]); in usb_dc_sam_usbc_isr_sta_dbg()
177 (regs->UESTA[ep_idx] & USBC_UESTA0_CURRBK(1)) > 0) { in usb_dc_sam_usbc_ep_curr_bank()
186 return (regs->UDCON & USBC_UDCON_DETACH) == 0; in usb_dc_is_attached()
191 int reg = regs->UERST; in usb_dc_ep_is_enabled()
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| /Zephyr-Core-3.4.0/soc/xtensa/intel_adsp/common/ |
| D | ipc.c | 40 volatile struct intel_adsp_ipc *regs = config->regs; in z_intel_adsp_ipc_isr() local
43 if (regs->tdr & INTEL_ADSP_IPC_BUSY) { in z_intel_adsp_ipc_isr()
47 uint32_t msg = regs->tdr & ~INTEL_ADSP_IPC_BUSY; in z_intel_adsp_ipc_isr()
48 uint32_t ext = regs->tdd; in z_intel_adsp_ipc_isr()
53 regs->tdr = INTEL_ADSP_IPC_BUSY; in z_intel_adsp_ipc_isr()
56 regs->tda = INTEL_ADSP_IPC_ACE1X_TDA_DONE; in z_intel_adsp_ipc_isr()
58 regs->tda = INTEL_ADSP_IPC_DONE; in z_intel_adsp_ipc_isr()
64 bool done = (regs->ida & INTEL_ADSP_IPC_DONE); in z_intel_adsp_ipc_isr()
81 regs->ida = INTEL_ADSP_IPC_DONE; in z_intel_adsp_ipc_isr()
97 config->regs->tdr = INTEL_ADSP_IPC_BUSY; in intel_adsp_ipc_init()
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| /Zephyr-Core-3.4.0/drivers/interrupt_controller/ |
| D | intc_dw.c | 40 volatile struct dw_ictl_registers * const regs = in dw_ictl_initialize() local
44 regs->irq_inten_l = 0U; in dw_ictl_initialize()
45 regs->irq_inten_h = 0U; in dw_ictl_initialize()
53 volatile struct dw_ictl_registers * const regs = in dw_ictl_isr() local
56 dw_ictl_dispatch_child_isrs(regs->irq_finalstatus_l, in dw_ictl_isr()
60 dw_ictl_dispatch_child_isrs(regs->irq_finalstatus_h, in dw_ictl_isr()
69 volatile struct dw_ictl_registers * const regs = in dw_ictl_intr_enable() local
73 regs->irq_inten_l |= (1 << irq); in dw_ictl_intr_enable()
75 regs->irq_inten_h |= (1 << (irq - 32)); in dw_ictl_intr_enable()
83 volatile struct dw_ictl_registers * const regs = in dw_ictl_intr_disable() local
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