Searched refs:pll_div (Results 1 – 3 of 3) sorted by relevance
| /Zephyr-Core-3.4.0/drivers/clock_control/ |
| D | clock_stm32f1.c | 38 uint32_t pll_source, pll_mul, pll_div; in config_pll_sysclock() local
66 pll_div = LL_RCC_PREDIV_DIV_2; in config_pll_sysclock()
73 pll_div = LL_RCC_PREDIV_DIV_1; in config_pll_sysclock()
84 pll_div = STM32_PLL_PREDIV - 1; in config_pll_sysclock()
92 pll_source = LL_RCC_PLLSOURCE_HSE | pll_div; in config_pll_sysclock()
95 pll_source = LL_RCC_PLLSOURCE_PLL2 | pll_div; in config_pll_sysclock()
120 uint32_t pll_mul, pll_div; in config_pll2() local
144 pll_div = ((STM32_PLL2_PREDIV - 1) << RCC_CFGR2_PREDIV2_Pos); in config_pll2()
151 LL_RCC_PLL_ConfigDomain_PLL2(pll_div, pll_mul); in config_pll2()
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| D | clock_stm32f0_f3.c | 26 uint32_t pll_source, pll_mul, pll_div; in config_pll_sysclock() local
46 pll_div = STM32_PLL_PREDIV - 1; in config_pll_sysclock()
65 LL_RCC_PLL_ConfigDomain_SYS(pll_source, pll_mul, pll_div); in config_pll_sysclock()
69 pll_source = LL_RCC_PLLSOURCE_HSE | pll_div; in config_pll_sysclock()
86 uint32_t pll_input_freq, pll_mul, pll_div; in get_pllout_frequency() local
106 pll_div = STM32_PLL_PREDIV - 1; in get_pllout_frequency()
125 return __LL_RCC_CALC_PLLCLK_FREQ(pll_input_freq, pll_mul, pll_div); in get_pllout_frequency()
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| D | clock_stm32l0_l1.c | 25 #define pll_div(v) z_pll_div(v) macro
68 pll_div(STM32_PLL_DIVISOR)); in config_pll_sysclock()
79 pll_div(STM32_PLL_DIVISOR)); in get_pllout_frequency()
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