| /Zephyr-Core-3.4.0/drivers/dma/ |
| D | dma_esp32_gdma.c | 67 struct dma_esp32_channel dma_channel[DMA_MAX_CHANNEL * 2]; member
108 struct dma_esp32_channel *dma_channel_rx = &config->dma_channel[rx_id]; in dma_esp32_isr_handle()
109 struct dma_esp32_channel *dma_channel_tx = &config->dma_channel[tx_id]; in dma_esp32_isr_handle()
125 struct dma_esp32_channel *dma_channel) in dma_esp32_enable_interrupt() argument
129 return esp_intr_enable(config->irq_src[dma_channel->channel_id]); in dma_esp32_enable_interrupt()
133 struct dma_esp32_channel *dma_channel) in dma_esp32_disable_interrupt() argument
137 return esp_intr_disable(config->irq_src[dma_channel->channel_id]); in dma_esp32_disable_interrupt()
141 struct dma_esp32_channel *dma_channel) in dma_esp32_enable_interrupt() argument
145 return esp_intr_enable(dma_channel->intr_handle); in dma_esp32_enable_interrupt()
149 struct dma_esp32_channel *dma_channel) in dma_esp32_disable_interrupt() argument
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| D | dma_xmc4xxx.c | 55 struct dma_xmc4xxx_channel *dma_channel; \
58 dma_channel = &dev_data->channels[channel]; \
62 if (dma_channel->cb) { \
63 dma_channel->cb(dev, dma_channel->user_data, channel, (ret)); \
101 struct dma_xmc4xxx_channel *dma_channel; in dma_xmc4xxx_isr() local
103 dma_channel = &dev_data->channels[i]; in dma_xmc4xxx_isr()
104 if (dma_channel->cb && dma_channel->dlr_line != DLR_LINE_UNSET && in dma_xmc4xxx_isr()
105 sr_overruns & BIT(dma_channel->dlr_line)) { in dma_xmc4xxx_isr()
108 dma_channel->cb(dev, dma_channel->user_data, i, -EIO); in dma_xmc4xxx_isr()
115 DLR->LNEN &= ~BIT(dma_channel->dlr_line); in dma_xmc4xxx_isr()
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| /Zephyr-Core-3.4.0/drivers/spi/ |
| D | spi_xmc4xxx.c | 51 uint32_t dma_channel; member
71 static void spi_xmc4xxx_dma_callback(const struct device *dev_dma, void *arg, uint32_t dma_channel, in spi_xmc4xxx_dma_callback() argument
77 LOG_ERR("DMA callback error on channel %d.", dma_channel); in spi_xmc4xxx_dma_callback()
80 if (dev_dma == data->dma_tx.dev_dma && dma_channel == data->dma_tx.dma_channel) { in spi_xmc4xxx_dma_callback()
83 dma_channel == data->dma_rx.dma_channel) { in spi_xmc4xxx_dma_callback()
86 LOG_ERR("DMA callback channel %d is not valid.", dma_channel); in spi_xmc4xxx_dma_callback()
407 ret = dma_config(dma_rx->dev_dma, dma_rx->dma_channel, &dma_rx->dma_cfg); in spi_xmc4xxx_transceive_dma()
416 ret = dma_start(dma_rx->dev_dma, dma_rx->dma_channel); in spi_xmc4xxx_transceive_dma()
437 ret = dma_config(dma_tx->dev_dma, dma_tx->dma_channel, &dma_tx->dma_cfg); in spi_xmc4xxx_transceive_dma()
448 ret = dma_start(dma_tx->dev_dma, dma_tx->dma_channel); in spi_xmc4xxx_transceive_dma()
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| D | spi_mcux_dspi.c | 32 uint32_t dma_channel; member
111 data->tx_dma_config.dma_channel); in spi_mcux_transfer_next_packet()
113 data->tx_dma_config.dma_channel); in spi_mcux_transfer_next_packet()
116 data->tx_dma_config.dma_channel, ret); in spi_mcux_transfer_next_packet()
125 data->rx_dma_config.dma_channel); in spi_mcux_transfer_next_packet()
127 data->rx_dma_config.dma_channel); in spi_mcux_transfer_next_packet()
130 data->rx_dma_config.dma_channel, ret); in spi_mcux_transfer_next_packet()
142 dma_start(data->tx_dma_config.dma_dev, data->tx_dma_config.dma_channel); in spi_mcux_transfer_next_packet()
217 dma_start(data->rx_dma_config.dma_dev, data->rx_dma_config.dma_channel); in spi_mcux_isr()
381 dma_config(data->tx_dma_config.dma_dev, data->tx_dma_config.dma_channel, in update_tx_dma()
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| /Zephyr-Core-3.4.0/drivers/i2s/ |
| D | i2s_ll_stm32.c | 511 static const struct device *get_dev_from_rx_dma_channel(uint32_t dma_channel);
512 static const struct device *get_dev_from_tx_dma_channel(uint32_t dma_channel);
550 ret = reload_dma(stream->dev_dma, stream->dma_channel, in dma_rx_callback()
634 ret = reload_dma(stream->dev_dma, stream->dma_channel, in dma_tx_callback()
735 active_dma_rx_channel[stream->dma_channel] = dev; in rx_stream_start()
737 ret = start_dma(stream->dev_dma, stream->dma_channel, in rx_stream_start()
779 active_dma_tx_channel[stream->dma_channel] = dev; in tx_stream_start()
781 ret = start_dma(stream->dev_dma, stream->dma_channel, in tx_stream_start()
807 dma_stop(stream->dev_dma, stream->dma_channel); in rx_stream_disable()
815 active_dma_rx_channel[stream->dma_channel] = NULL; in rx_stream_disable()
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| D | i2s_mcux_sai.c | 69 uint32_t dma_channel; member
145 LOG_DBG("Stopping DMA channel %u for TX stream", strm->dma_channel); in i2s_tx_stream_disable()
151 dma_stop(dev_dma, strm->dma_channel); in i2s_tx_stream_disable()
185 LOG_DBG("Stopping RX stream & DMA channel %u", strm->dma_channel); in i2s_rx_stream_disable()
186 dma_stop(dev_dma, strm->dma_channel); in i2s_rx_stream_disable()
238 ret = dma_reload(dev_data->dev_dma, strm->dma_channel, in i2s_tx_reload_multiple_dma_blocks()
315 dma_start(dev_data->dev_dma, strm->dma_channel); in i2s_dma_tx_callback()
393 strm->dma_channel, in i2s_dma_rx_callback()
416 strm->dma_channel); in i2s_dma_rx_callback()
777 dma_config(dev_dma, strm->dma_channel, &strm->dma_cfg); in i2s_tx_stream_start()
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| D | i2s_sam_ssc.c | 81 uint32_t dma_channel; member
105 static const struct device *get_dev_from_dma_channel(uint32_t dma_channel);
250 ret = reload_dma(dev_cfg->dev_dma, stream->dma_channel, in dma_rx_callback()
311 ret = reload_dma(dev_cfg->dev_dma, stream->dma_channel, in dma_tx_callback()
662 ret = start_dma(dev_dma, stream->dma_channel, &dma_cfg, in rx_stream_start()
714 ret = start_dma(dev_dma, stream->dma_channel, &dma_cfg, in tx_stream_start()
737 dma_stop(dev_dma, stream->dma_channel); in rx_stream_disable()
749 dma_stop(dev_dma, stream->dma_channel); in tx_stream_disable()
1003 static const struct device *get_dev_from_dma_channel(uint32_t dma_channel) in get_dev_from_dma_channel() argument
1030 .dma_channel = DT_INST_DMAS_CELL_BY_NAME(0, rx, channel),
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| D | i2s_ll_stm32.h | 38 uint32_t dma_channel; member
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| /Zephyr-Core-3.4.0/drivers/serial/ |
| D | uart_xmc4xxx.c | 42 uint32_t dma_channel; member
498 if (dma_get_status(data->dma_rx.dma_dev, data->dma_rx.dma_channel, &stat) == 0) { in uart_xmc4xxx_async_rx_timeout()
525 if (!dma_get_status(data->dma_tx.dma_dev, data->dma_tx.dma_channel, &stat)) { in uart_xmc4xxx_async_tx_abort()
529 dma_stop(data->dma_tx.dma_dev, data->dma_tx.dma_channel); in uart_xmc4xxx_async_tx_abort()
636 ret = dma_config(data->dma_tx.dma_dev, data->dma_tx.dma_channel, &data->dma_tx.dma_cfg); in uart_xmc4xxx_async_tx()
652 return dma_start(data->dma_tx.dma_dev, data->dma_tx.dma_channel); in uart_xmc4xxx_async_tx()
678 ret = dma_config(data->dma_rx.dma_dev, data->dma_rx.dma_channel, &data->dma_rx.dma_cfg); in uart_xmc4xxx_async_rx_enable()
688 return dma_start(data->dma_rx.dma_dev, data->dma_rx.dma_channel); in uart_xmc4xxx_async_rx_enable()
703 __ASSERT_NO_MSG(channel == data->dma_rx.dma_channel); in uart_xmc4xxx_dma_rx_cb()
717 dma_stop(data->dma_rx.dma_dev, data->dma_rx.dma_channel); in uart_xmc4xxx_dma_rx_cb()
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| D | uart_mcux_lpuart.c | 30 const uint32_t dma_channel; member
471 config->rx_dma_config.dma_channel, in mcux_lpuart_async_rx_flush()
517 config->rx_dma_config.dma_channel); in mcux_lpuart_rx_disable()
556 config->rx_dma_config.dma_channel, in configure_and_start_rx_dma()
563 ret = dma_start(config->rx_dma_config.dma_dev, config->rx_dma_config.dma_channel); in configure_and_start_rx_dma()
566 config->rx_dma_config.dma_channel, in configure_and_start_rx_dma()
584 config->rx_dma_config.dma_channel, in uart_mcux_lpuart_dma_replace_rx_buffer()
619 if (channel == config->tx_dma_config.dma_channel) { in dma_callback()
623 } else if (channel == config->rx_dma_config.dma_channel) { in dma_callback()
679 config->tx_dma_config.dma_channel, in mcux_lpuart_tx()
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| D | uart_stm32.h | 62 uint32_t dma_channel; member
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| D | uart_stm32.c | 976 data->dma_rx.dma_channel, &stat) == 0) { in uart_stm32_dma_rx_flush()
1146 dma_stop(data->dma_rx.dma_dev, data->dma_rx.dma_channel); in uart_stm32_async_rx_disable()
1183 data->dma_tx.dma_channel, &stat)) { in uart_stm32_dma_tx_cb()
1211 dma_reload(data->dma_rx.dma_dev, data->dma_rx.dma_channel, in uart_stm32_dma_replace_buffer()
1216 dma_start(data->dma_rx.dma_dev, data->dma_rx.dma_channel); in uart_stm32_dma_replace_buffer()
1292 ret = dma_config(data->dma_tx.dma_dev, data->dma_tx.dma_channel, in uart_stm32_async_tx()
1300 if (dma_start(data->dma_tx.dma_dev, data->dma_tx.dma_channel)) { in uart_stm32_async_tx()
1348 ret = dma_config(data->dma_rx.dma_dev, data->dma_rx.dma_channel, in uart_stm32_async_rx_enable()
1356 if (dma_start(data->dma_rx.dma_dev, data->dma_rx.dma_channel)) { in uart_stm32_async_rx_enable()
1392 data->dma_tx.dma_channel, &stat)) { in uart_stm32_async_tx_abort()
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| /Zephyr-Core-3.4.0/drivers/adc/ |
| D | adc_mcux_adc16.c | 52 uint32_t dma_channel; member
219 dma_stop(data->dev_dma, data->adc_dma_config.dma_channel); in start_read()
273 dma_start(data->dev_dma, data->adc_dma_config.dma_channel); in mcux_adc16_start_channel()
292 dma_config(data->dev_dma, data->adc_dma_config.dma_channel, in adc_context_start_sampling()
417 data->adc_dma_config.dma_channel = in mcux_adc16_init()
422 data->adc_dma_config.dma_channel = in mcux_adc16_init()
425 if (data->adc_dma_config.dma_channel == -EINVAL) { in mcux_adc16_init()
429 LOG_DBG("dma allocated channel %d", data->adc_dma_config.dma_channel); in mcux_adc16_init()
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| /Zephyr-Core-3.4.0/drivers/i2c/ |
| D | i2c_sam0.c | 45 uint8_t dma_channel; member
101 if (cfg->dma_channel != 0xFF) { in i2c_sam0_terminate_on_error()
102 dma_stop(cfg->dma_dev, cfg->dma_channel); in i2c_sam0_terminate_on_error()
263 if (cfg->dma_channel == 0xFF) { in i2c_sam0_dma_write_start()
291 retval = dma_config(cfg->dma_dev, cfg->dma_channel, &dma_cfg); in i2c_sam0_dma_write_start()
298 retval = dma_start(cfg->dma_dev, cfg->dma_channel); in i2c_sam0_dma_write_start()
355 if (cfg->dma_channel == 0xFF) { in i2c_sam0_dma_read_start()
384 retval = dma_config(cfg->dma_dev, cfg->dma_channel, &dma_cfg); in i2c_sam0_dma_read_start()
391 retval = dma_start(cfg->dma_dev, cfg->dma_channel); in i2c_sam0_dma_read_start()
775 .dma_channel = ATMEL_SAM0_DT_INST_DMA_CHANNEL(n, rx),
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