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/Zephyr-Core-2.7.6/subsys/net/lib/http/
Dhttp_parser_url.c382 int http_parse_host(const char *buf, struct http_parser_url *u, in http_parse_host() argument
389 buflen = u->field_data[UF_HOST].off + u->field_data[UF_HOST].len; in http_parse_host()
390 __ASSERT_NO_MSG(u->field_set & (1 << UF_HOST)); in http_parse_host()
392 u->field_data[UF_HOST].len = 0U; in http_parse_host()
396 for (p = buf + u->field_data[UF_HOST].off; p < buf + buflen; p++) { in http_parse_host()
406 u->field_data[UF_HOST].off = p - buf; in http_parse_host()
408 u->field_data[UF_HOST].len++; in http_parse_host()
413 u->field_data[UF_HOST].off = p - buf; in http_parse_host()
415 u->field_data[UF_HOST].len++; in http_parse_host()
420 u->field_data[UF_HOST].len++; in http_parse_host()
[all …]
/Zephyr-Core-2.7.6/samples/boards/intel_s1000_crb/i2s/
DCMakeLists.txt15 target_link_libraries(app PUBLIC -Wl,-u,__extendsfdf2)
16 target_link_libraries(app PUBLIC -Wl,-u,__truncdfsf2)
17 target_link_libraries(app PUBLIC -Wl,-u,__divsf3)
18 target_link_libraries(app PUBLIC -Wl,-u,__divdf3)
19 target_link_libraries(app PUBLIC -Wl,-u,__adddf3)
20 target_link_libraries(app PUBLIC -Wl,-u,__subdf3)
21 target_link_libraries(app PUBLIC -Wl,-u,__ieee754_sqrtf)
22 target_link_libraries(app PUBLIC -Wl,-u,__ieee754_remainderf)
23 target_link_libraries(app PUBLIC -Wl,-u,__nedf2)
/Zephyr-Core-2.7.6/tests/bluetooth/uuid/src/
Dmain.c56 } u; in test_uuid_create() local
59 zassert_true(bt_uuid_create(&u.uuid, le16, sizeof(le16)), in test_uuid_create()
63 zassert_true(bt_uuid_cmp(&u.uuid, BT_UUID_DECLARE_16(0x0001)) == 0, in test_uuid_create()
67 zassert_true(bt_uuid_cmp(&u.uuid, &le_128.uuid) == 0, in test_uuid_create()
71 zassert_false(bt_uuid_cmp(&u.uuid, BT_UUID_DECLARE_16(0x0100)) == 0, in test_uuid_create()
75 zassert_true(bt_uuid_create(&u.uuid, be16, sizeof(be16)), in test_uuid_create()
79 zassert_false(bt_uuid_cmp(&u.uuid, BT_UUID_DECLARE_16(0x0001)) == 0, in test_uuid_create()
83 zassert_false(bt_uuid_cmp(&u.uuid, &le_128.uuid) == 0, in test_uuid_create()
87 zassert_true(bt_uuid_cmp(&u.uuid, BT_UUID_DECLARE_16(0x0100)) == 0, in test_uuid_create()
/Zephyr-Core-2.7.6/subsys/tracing/sysview/
DSYSVIEW_Zephyr.txt9 NamedType TimeOut *="%u ticks" 0=TIMEOUT_NO_WAIT 4294967295=FOREVER
33 34 k_busy_wait Timeout=%u us
35 35 irq_enable irq=%u
36 36 irq_disable irq=%u
42 40 k_sem_init sem=%I, initial_count=%u, | Returns %ErrCodePosix
60 55 k_stack_init stack=%I, buffer=%p, num_entries=%u
65 59 k_msgq_init msgq=%I, buffer=%p, msg_size=%u, max_msgs=%us
79 71 k_pipe_init pipe=%I, buffer=%p, size=%u
81 73 k_pipe_put pipe=%I, data=%p, bytes_to_write=%u, bytes_written=%u, min_xfer=%u, …
82 74 k_pipe_get pipe=%I, data=%p, bytes_to_read=%u, bytes_read=%u, min_xfer=%u, Time…
[all …]
/Zephyr-Core-2.7.6/samples/posix/eventfd/src/
Dmain.c28 uint64_t u; in writer() local
33 u = strtoull(g_argv[j], NULL, 0); in writer()
34 s = write(efd, &u, sizeof(uint64_t)); in writer()
44 uint64_t u; in reader() local
50 s = read(efd, &u, sizeof(uint64_t)); in reader()
55 (unsigned long long)u, (unsigned long long)u); in reader()
/Zephyr-Core-2.7.6/tests/net/lib/http_header_fields/src/
Dmain.c47 struct http_parser_url u; member
56 .u = { .field_set = (1 << UF_SCHEMA) | (1 << UF_HOST) | (1 << UF_PATH),
73 .u = { .field_set = (1 << UF_SCHEMA) | (1 << UF_HOST) |
91 .u = { .field_set = (1 << UF_HOST) | (1 << UF_PORT),
115 .u = { .field_set = (1 << UF_SCHEMA) | (1 << UF_HOST) | (1 << UF_PATH),
132 .u = { .field_set = (1 << UF_SCHEMA) | (1 << UF_HOST) |
150 .u = { .field_set = (1 << UF_HOST) | (1 << UF_PORT),
167 .u = { .field_set = (1 << UF_SCHEMA) | (1 << UF_HOST) | (1 << UF_PATH),
187 .u = { .field_set = (1<<UF_SCHEMA) | (1<<UF_HOST) | (1<<UF_PATH) |
205 .u = { .field_set = (1<<UF_PATH) | (1<<UF_QUERY),
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/Zephyr-Core-2.7.6/soc/arm/microchip_mec/mec172x/reg/
Dmec172x_qspi.h25 #define MCHP_QMSPI_SPI_MODE0 0u
45 #define MCHP_QMSPI_M_ACT_SRST_OFS 0u
141 #define MCHP_QMSPI_M_CPHA_MOSI_CE1 0u
147 #define MCHP_QMSPI_M_CPHA_MISO_CE1 0u
154 #define MCHP_QMSPI_M_SIG_MODE0_VAL 0u
158 #define MCHP_QMSPI_M_SIG_MODE0 0u
165 #define MCHP_QMSPI_M_CS0 SHLU32(0u, 12)
176 #define MCHP_QMSPI_C_IFM_1X 0u
181 #define MCHP_QMSPI_C_TX_DIS 0u
187 #define MCHP_QMSPI_C_TX_DMA_DIS 0u
[all …]
Dmec172x_espi_iom.h31 #define MCHP_ESPI_GBL_CAP1_MAX_FREQ_POS 0u
41 #define MCHP_ESPI_GBL_CAP1_ALERT_ON_IO1 0u
45 #define MCHP_ESPI_GBL_CAP1_IO_MODE0_1 0u
105 #define MCHP_ESPI_FC_CAP_SHARE_MAF_ONLY 0u
138 #define MCHP_ESPI_RST_ISTS_POS 0u
149 #define MCHP_ESPI_PLTRST_SRC_POS 0u
178 #define MCHP_ESPI_VW_ERR_STS_FATAL_POS 0u
203 #define MCHP_ESPI_PC_LC_LEN_POS 0u
247 #define MCHP_ESPI_LTR_STS_TX_DONE_POS 0u /* RW1C */
256 #define MCHP_ESPI_LTR_IEN_TX_DONE_POS 0u
[all …]
Dmec172x_espi_vw.h15 #define ESPI_M2SW0_OFS 0u
21 #define ESPI_M2SW0_MTOS_SRC_ESPI_RST 0u
88 #define ESPI_S2MW0_STOM_SRC_ESPI_RST 0u
113 #define ESPI_S2MW1_SRC0_POS 0u
144 #define MSVW_INDEX_OFS 0u
156 #define SMVW_INDEX_OFS 0u
166 #define MEC_MSVW_SRC0_IRQ_SEL_POS 0u
195 #define MEC_MSVW_SRC0_POS 0u
224 MSVW_SRC0 = 0u,
231 SMVW_SRC0 = 0u,
[all …]
/Zephyr-Core-2.7.6/lib/os/
Dcbprintf_packaged.c81 } u; in cbprintf_via_va_list() local
84 u.__ap.__stack = buf; in cbprintf_via_va_list()
85 u.__ap.__gr_top = NULL; in cbprintf_via_va_list()
86 u.__ap.__vr_top = NULL; in cbprintf_via_va_list()
87 u.__ap.__gr_offs = 0; in cbprintf_via_va_list()
88 u.__ap.__vr_offs = 0; in cbprintf_via_va_list()
90 return cbvprintf(out, ctx, fmt, u.ap); in cbprintf_via_va_list()
117 } u; in cbprintf_via_va_list() local
120 u.__ap.overflow_arg_area = buf; in cbprintf_via_va_list()
121 u.__ap.reg_save_area = NULL; in cbprintf_via_va_list()
[all …]
/Zephyr-Core-2.7.6/soc/arm/cypress/psoc6/
Dsoc.c55 Cy_SysClk_ClkFastSetDivider(0u); in Cy_SysClk_ClkFastInit()
64 Cy_SysClk_ClkHfSetSource(0u, CY_SYSCLK_CLKHF_IN_CLKPATH0); in Cy_SysClk_ClkHf0Init()
65 Cy_SysClk_ClkHfSetDivider(0u, CY_SYSCLK_CLKHF_NO_DIVIDE); in Cy_SysClk_ClkHf0Init()
66 Cy_SysClk_ClkHfEnable(0u); in Cy_SysClk_ClkHf0Init()
80 Cy_SysClk_ClkPathSetSource(0u, CY_SYSCLK_CLKPATH_IN_IMO); in Cy_SysClk_ClkPath0Init()
104 Cy_SysClk_ClkSlowSetDivider(0u); in Cy_SysClk_ClkSlowInit()
369 Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 0u, 0u); in Cy_SystemInit()
370 Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 0u); in Cy_SystemInit()
/Zephyr-Core-2.7.6/soc/arm/microchip_mec/common/reg/
Dmec_adc.h18 #define MCHP_ADC_CTRL_REG_OFS 0u
33 #define MCHP_ADC_DELAY_START_POS 0u
80 #define MCHP_ADC_CH_VREF_SEL_PAD(n) 0u
93 #define MCHP_ADC_VREF_CTRL_PAD_UNUSED_FLOAT 0u
104 #define MCHP_ADC_SAR_CTRL_SELDIFF_DIS 0u
114 #define MCHP_ADC_SAR_CTRL_SHIFTD_DIS 0u
Dmec_ps2.h24 #define MCHP_PS2_CTRL_TR_POS 0u
25 #define MCHP_PS2_CTRL_TR_RX 0u
36 #define MCHP_PS2_CTRL_PAR_ODD 0u
45 #define MCHP_PS2_CTRL_STOP_ACT_HI 0u
Dmec_uart.h26 #define MCHP_UART_RTXB_OFS 0u
27 #define MCHP_UART_BRGD_LSB_OFS 0u
137 #define MCHP_UART_LD_CFG_INTCLK 0u
138 #define MCHP_UART_LD_CFG_NO_INVERT 0u
139 #define MCHP_UART_LD_CFG_RESET_SYS 0u
Dmec_wdt.h20 #define MCHP_WDT_CTRL_EN_POS 0u
44 #define MCHP_WDT_CTRL_MODE_RESET 0u
59 #define MCHP_WDT_STS_EVENT_IRQ_POS 0u
65 #define MCHP_WDT_IEN_EVENT_IRQ_POS 0u
Dmec_pwm.h17 #define MCHP_PWM_COUNT_ON_REG_OFS 0u
35 #define MCHP_PWM_CFG_CLK_SEL_48M 0u
42 #define MCHP_PWM_CFG_ON_POL_HI 0u
Dmec_kbc.h16 #define MCHP_KBC_STS_OBF_POS 0u
36 #define MCHP_KBC_CTRL_UD3_POS 0u
53 #define MCHP_KBC_PCOBF_EN_POS 0u
57 #define MCHP_KBC_PORT92_EN_POS 0u
Dmec_acpi_ec.h58 #define MCHP_ACPI_PM1_EN1_REG_MASK 0u
71 #define MCHP_ACPI_PM1_CTRL1_REG_MASK 0u
85 #define MCHP_ACPI_PM1_CTRL21_REG_MASK 0u
90 #define MCHP_ACPI_PM1_CTRL22_REG_MASK 0u
/Zephyr-Core-2.7.6/boards/arm/ubx_evkannab1_nrf52832/
DKconfig.board1 # u-blox EVK-ANNA-B1 board configuration
3 # Copyright (c) 2021 u-blox AG
7 bool "u-blox EVK-ANNA-B1"
/Zephyr-Core-2.7.6/boards/arm/ubx_evkninab1_nrf52832/
DKconfig.board1 # u-blox EVK-NINA-B1 board configuration
3 # Copyright (c) 2021 u-blox AG
7 bool "u-blox EVK-NINA-B1"
/Zephyr-Core-2.7.6/drivers/modem/
DKconfig.ublox-sara-r41 # u-blox SARA R4 driver options
7 bool "Enable u-blox SARA modem driver"
15 Choose this setting to enable u-blox SARA-R4 LTE-CatM1/NB-IoT modem
21 bool "u-blox SARA variant selection"
25 bool "u-blox SARA-R4"
30 bool "u-blox SARA-U2"
42 int "Stack size for the u-blox SARA-R4 modem driver RX thread"
45 This stack is used by the u-blox SARA-R4 RX thread.
48 int "Stack size for the u-blox SARA-R4 modem driver work queue"
85 int "u-blox SARA-R4 driver init priority"
[all …]
/Zephyr-Core-2.7.6/boards/arm/ubx_bmd330eval_nrf52810/
DKconfig.board3 # Copyright (c) 2021 u-blox AG
7 bool "u-blox BMD-330-EVAL"
/Zephyr-Core-2.7.6/boards/arm/ubx_bmd360eval_nrf52811/
DKconfig.board3 # Copyright (c) 2021 u-blox AG
7 bool "u-blox BMD-360-EVAL"
/Zephyr-Core-2.7.6/boards/arm/ubx_bmd340eval_nrf52840/
DKconfig.board3 # Copyright (c) 2021 u-blox AG
7 bool "u-blox BMD-340-EVAL"
/Zephyr-Core-2.7.6/boards/arm/ubx_evkninab4_nrf52833/
DKconfig.board3 # Copyright (c) 2021 u-blox AG
7 bool "u-blox EVK-NINA-B4"

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