| /Zephyr-latest/drivers/dma/ |
| D | dma_esp32_gdma.c | 73 struct dma_esp32_channel dma_channel[DMA_MAX_CHANNEL * 2]; member
124 struct dma_esp32_channel *dma_channel_rx = &config->dma_channel[rx_id]; in dma_esp32_isr_handle()
125 struct dma_esp32_channel *dma_channel_tx = &config->dma_channel[tx_id]; in dma_esp32_isr_handle()
140 static int dma_esp32_config_descriptor(struct dma_esp32_channel *dma_channel, in dma_esp32_config_descriptor() argument
149 dma_descriptor_t *desc_iter = dma_channel->desc_list; in dma_esp32_config_descriptor()
153 if (dma_channel->dir == DMA_TX) { in dma_esp32_config_descriptor()
164 if (dma_channel->dir == DMA_TX) { in dma_esp32_config_descriptor()
189 if (dma_channel->dir == DMA_TX) { in dma_esp32_config_descriptor()
202 if (dma_channel->dir == DMA_TX) { in dma_esp32_config_descriptor()
214 memset(dma_channel->desc_list, 0, sizeof(dma_channel->desc_list)); in dma_esp32_config_descriptor()
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| D | dma_xmc4xxx.c | 83 struct dma_xmc4xxx_channel *dma_channel; \
86 dma_channel = &dev_data->channels[channel]; \
90 if (dma_channel->cb) { \
91 dma_channel->cb(dev, dma_channel->user_data, channel, (ret)); \
129 struct dma_xmc4xxx_channel *dma_channel; in dma_xmc4xxx_isr() local
131 dma_channel = &dev_data->channels[i]; in dma_xmc4xxx_isr()
132 if (dma_channel->dlr_line != DLR_LINE_UNSET && in dma_xmc4xxx_isr()
133 sr_overruns & BIT(dma_channel->dlr_line)) { in dma_xmc4xxx_isr()
140 DLR->LNEN &= ~BIT(dma_channel->dlr_line); in dma_xmc4xxx_isr()
141 DLR->LNEN |= BIT(dma_channel->dlr_line); in dma_xmc4xxx_isr()
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| /Zephyr-latest/drivers/flash/ |
| D | soc_flash_silabs_series2.c | 28 uint32_t dma_channel; member
108 err = dma_config(dev_data->dma_dev, dev_data->dma_channel, &dev_data->dma_cfg); in flash_silabs_read_dma()
113 err = dma_start(dev_data->dma_dev, dev_data->dma_channel); in flash_silabs_read_dma()
172 LDMA->IEN_CLR = BIT(dev_data->dma_channel); in flash_silabs_write()
173 LDMA->CHDONE_CLR = BIT(dev_data->dma_channel); in flash_silabs_write()
174 ret = MSC_WriteWordDma(dev_data->dma_channel, address, data, size); in flash_silabs_write()
282 dev_data->dma_channel = dma_request_channel(dev_data->dma_dev, NULL); in flash_silabs_init()
306 .dma_channel = -1,
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| /Zephyr-latest/drivers/spi/ |
| D | spi_xmc4xxx.c | 52 uint32_t dma_channel; member
72 static void spi_xmc4xxx_dma_callback(const struct device *dev_dma, void *arg, uint32_t dma_channel, in spi_xmc4xxx_dma_callback() argument
78 LOG_ERR("DMA callback error on channel %d.", dma_channel); in spi_xmc4xxx_dma_callback()
81 if (dev_dma == data->dma_tx.dev_dma && dma_channel == data->dma_tx.dma_channel) { in spi_xmc4xxx_dma_callback()
84 dma_channel == data->dma_rx.dma_channel) { in spi_xmc4xxx_dma_callback()
87 LOG_ERR("DMA callback channel %d is not valid.", dma_channel); in spi_xmc4xxx_dma_callback()
409 ret = dma_config(dma_rx->dev_dma, dma_rx->dma_channel, &dma_rx->dma_cfg); in spi_xmc4xxx_transceive_dma()
418 ret = dma_start(dma_rx->dev_dma, dma_rx->dma_channel); in spi_xmc4xxx_transceive_dma()
439 ret = dma_config(dma_tx->dev_dma, dma_tx->dma_channel, &dma_tx->dma_cfg); in spi_xmc4xxx_transceive_dma()
450 ret = dma_start(dma_tx->dev_dma, dma_tx->dma_channel); in spi_xmc4xxx_transceive_dma()
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| D | spi_mcux_dspi.c | 33 uint32_t dma_channel; member
112 data->tx_dma_config.dma_channel); in spi_mcux_transfer_next_packet()
114 data->tx_dma_config.dma_channel); in spi_mcux_transfer_next_packet()
117 data->tx_dma_config.dma_channel, ret); in spi_mcux_transfer_next_packet()
126 data->rx_dma_config.dma_channel); in spi_mcux_transfer_next_packet()
128 data->rx_dma_config.dma_channel); in spi_mcux_transfer_next_packet()
131 data->rx_dma_config.dma_channel, ret); in spi_mcux_transfer_next_packet()
143 dma_start(data->tx_dma_config.dma_dev, data->tx_dma_config.dma_channel); in spi_mcux_transfer_next_packet()
218 dma_start(data->rx_dma_config.dma_dev, data->rx_dma_config.dma_channel); in spi_mcux_isr()
382 dma_config(data->tx_dma_config.dma_dev, data->tx_dma_config.dma_channel, in update_tx_dma()
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| D | spi_silabs_eusart.c | 42 struct dma_channel { struct
53 struct dma_channel dma_chan_rx; argument
54 struct dma_channel dma_chan_tx;
332 struct dma_channel *channel, in spi_silabs_dma_config()
439 static void spi_eusart_reset_desc(struct dma_channel *channel) in spi_eusart_reset_desc()
452 struct dma_channel *channel, in spi_eusart_prepare_dma_channel()
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| /Zephyr-latest/drivers/i2s/ |
| D | i2s_ll_stm32.c | 505 static const struct device *get_dev_from_rx_dma_channel(uint32_t dma_channel);
506 static const struct device *get_dev_from_tx_dma_channel(uint32_t dma_channel);
544 ret = reload_dma(stream->dev_dma, stream->dma_channel, in dma_rx_callback()
652 ret = reload_dma(stream->dev_dma, stream->dma_channel, in dma_tx_callback()
759 active_dma_rx_channel[stream->dma_channel] = dev; in rx_stream_start()
761 ret = start_dma(stream->dev_dma, stream->dma_channel, in rx_stream_start()
815 active_dma_tx_channel[stream->dma_channel] = dev; in tx_stream_start()
817 ret = start_dma(stream->dev_dma, stream->dma_channel, in tx_stream_start()
862 dma_stop(stream->dev_dma, stream->dma_channel); in rx_stream_disable()
870 active_dma_rx_channel[stream->dma_channel] = NULL; in rx_stream_disable()
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| D | i2s_esp32.c | 41 uint32_t dma_channel; member
153 err = dma_reload(stream->dma_dev, stream->dma_channel, (uint32_t)src, (uint32_t)dst, in i2s_esp32_restart_dma()
156 LOG_ERR("Error reloading DMA channel[%d]: %d", (int)stream->dma_channel, err); in i2s_esp32_restart_dma()
164 err = dma_start(stream->dma_dev, stream->dma_channel); in i2s_esp32_restart_dma()
166 LOG_ERR("Error starting DMA channel[%d]: %d", (int)stream->dma_channel, err); in i2s_esp32_restart_dma()
210 err = dma_config(stream->dma_dev, stream->dma_channel, &dma_cfg); in i2s_esp32_start_dma()
212 LOG_ERR("Error configuring DMA channel[%d]: %d", (int)stream->dma_channel, err); in i2s_esp32_start_dma()
221 err = dma_start(stream->dma_dev, stream->dma_channel); in i2s_esp32_start_dma()
223 LOG_ERR("Error starting DMA channel[%d]: %d", (int)stream->dma_channel, err); in i2s_esp32_start_dma()
299 dma_stop(stream->dma_dev, stream->dma_channel); in i2s_esp32_rx_stop_transfer()
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| D | i2s_mcux_sai.c | 75 uint32_t dma_channel; member
145 LOG_DBG("Stopping DMA channel %u for TX stream", strm->dma_channel); in i2s_tx_stream_disable()
150 dma_stop(dev_dma, strm->dma_channel); in i2s_tx_stream_disable()
180 LOG_DBG("Stopping RX stream & DMA channel %u", strm->dma_channel); in i2s_rx_stream_disable()
181 dma_stop(dev_dma, strm->dma_channel); in i2s_rx_stream_disable()
229 ret = dma_reload(dev_data->dev_dma, strm->dma_channel, (uint32_t)buffer, in i2s_tx_reload_multiple_dma_blocks()
391 ret = dma_reload(dev_data->dev_dma, strm->dma_channel, in i2s_dma_rx_callback()
715 dma_config(dev_dma, strm->dma_channel, &strm->dma_cfg); in i2s_tx_stream_start()
732 ret = dma_start(dev_dma, strm->dma_channel); in i2s_tx_stream_start()
795 dma_config(dev_dma, strm->dma_channel, &strm->dma_cfg); in i2s_rx_stream_start()
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| D | i2s_sam_ssc.c | 81 uint32_t dma_channel; member
105 static const struct device *get_dev_from_dma_channel(uint32_t dma_channel);
250 ret = reload_dma(dev_cfg->dev_dma, stream->dma_channel, in dma_rx_callback()
311 ret = reload_dma(dev_cfg->dev_dma, stream->dma_channel, in dma_tx_callback()
662 ret = start_dma(dev_dma, stream->dma_channel, &dma_cfg, in rx_stream_start()
714 ret = start_dma(dev_dma, stream->dma_channel, &dma_cfg, in tx_stream_start()
737 dma_stop(dev_dma, stream->dma_channel); in rx_stream_disable()
749 dma_stop(dev_dma, stream->dma_channel); in tx_stream_disable()
1003 static const struct device *get_dev_from_dma_channel(uint32_t dma_channel) in get_dev_from_dma_channel() argument
1030 .dma_channel = DT_INST_DMAS_CELL_BY_NAME(0, rx, channel),
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| D | i2s_ll_stm32.h | 30 uint32_t dma_channel; member
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| /Zephyr-latest/drivers/display/ |
| D | display_renesas_lcdc.c | 76 int dma_channel; member
241 data->dma_channel = dma_request_channel(data->dma, NULL); in display_smartbond_dma_config()
242 if (data->dma_channel < 0) { in display_smartbond_dma_config()
292 dma_release_channel(data->dma, data->dma_channel); in display_smartbond_dma_deconfig()
496 if (dma_config(data->dma, data->dma_channel, &data->dma_cfg)) { in display_smartbond_read()
502 if (dma_start(data->dma, data->dma_channel)) { in display_smartbond_read()
514 if (dma_stop(data->dma, data->dma_channel)) { in display_smartbond_read()
565 if (dma_config(data->dma, data->dma_channel, &data->dma_cfg)) { in display_smartbond_write()
571 if (dma_start(data->dma, data->dma_channel)) { in display_smartbond_write()
583 if (dma_stop(data->dma, data->dma_channel)) { in display_smartbond_write()
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| /Zephyr-latest/drivers/serial/ |
| D | uart_xmc4xxx.c | 42 uint32_t dma_channel; member
443 if (dma_get_status(data->dma_rx.dma_dev, data->dma_rx.dma_channel, &stat) == 0) { in async_evt_rx_stopped()
525 if (dma_get_status(data->dma_rx.dma_dev, data->dma_rx.dma_channel, &stat) == 0) { in uart_xmc4xxx_async_rx_timeout()
552 if (!dma_get_status(data->dma_tx.dma_dev, data->dma_tx.dma_channel, &stat)) { in uart_xmc4xxx_async_tx_abort()
556 dma_stop(data->dma_tx.dma_dev, data->dma_tx.dma_channel); in uart_xmc4xxx_async_tx_abort()
669 ret = dma_config(data->dma_tx.dma_dev, data->dma_tx.dma_channel, &data->dma_tx.dma_cfg); in uart_xmc4xxx_async_tx()
685 return dma_start(data->dma_tx.dma_dev, data->dma_tx.dma_channel); in uart_xmc4xxx_async_tx()
711 ret = dma_config(data->dma_rx.dma_dev, data->dma_rx.dma_channel, &data->dma_rx.dma_cfg); in uart_xmc4xxx_async_rx_enable()
721 return dma_start(data->dma_rx.dma_dev, data->dma_rx.dma_channel); in uart_xmc4xxx_async_rx_enable()
732 __ASSERT_NO_MSG(channel == data->dma_rx.dma_channel); in uart_xmc4xxx_dma_rx_cb()
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| D | uart_ifx_cat1.c | 35 uint32_t dma_channel; member
510 ret = dma_config(dma_stream->dev, dma_stream->dma_channel, &dma_stream->dma_cfg); in ifx_cat1_uart_async_dma_config_buffer()
513 ret = dma_start(dma_stream->dev, dma_stream->dma_channel); in ifx_cat1_uart_async_dma_config_buffer()
568 err = dma_stop(data->async.dma_tx.dev, data->async.dma_tx.dma_channel); in ifx_cat1_uart_async_tx_abort()
574 err = dma_get_status(data->async.dma_tx.dev, data->async.dma_tx.dma_channel, &stat); in ifx_cat1_uart_async_tx_abort()
603 dma_stop(data->async.dma_tx.dev, data->async.dma_tx.dma_channel); in dma_callback_tx_done()
618 dma_stop(data->async.dma_tx.dev, data->async.dma_tx.dma_channel); in dma_callback_tx_done()
712 if (dma_get_status(data->async.dma_rx.dev, data->async.dma_rx.dma_channel, &stat) == 0) { in async_evt_rx_stopped()
753 err = dma_get_status(data->async.dma_rx.dev, data->async.dma_rx.dma_channel, &dma_status); in ifx_cat1_uart_async_rx_enable()
794 dma_stop(data->async.dma_rx.dev, data->async.dma_rx.dma_channel); in dma_callback_rx_rdy()
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| D | uart_mcux_lpuart.c | 50 const uint32_t dma_channel; member
515 config->rx_dma_config.dma_channel, in mcux_lpuart_async_rx_flush()
562 config->rx_dma_config.dma_channel); in mcux_lpuart_rx_disable()
601 config->rx_dma_config.dma_channel, in configure_and_start_rx_dma()
608 ret = dma_start(config->rx_dma_config.dma_dev, config->rx_dma_config.dma_channel); in configure_and_start_rx_dma()
611 config->rx_dma_config.dma_channel, in configure_and_start_rx_dma()
630 dma_reload(config->rx_dma_config.dma_dev, config->rx_dma_config.dma_channel, in uart_mcux_lpuart_dma_replace_rx_buffer()
665 if (channel == config->tx_dma_config.dma_channel) { in dma_callback()
669 } else if (channel == config->rx_dma_config.dma_channel) { in dma_callback()
740 config->tx_dma_config.dma_channel, in mcux_lpuart_tx()
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| D | uart_silabs_usart.c | 33 uint32_t dma_channel; member
420 if (!dma_get_status(data->dma_rx.dma_dev, data->dma_rx.dma_channel, &stat)) { in uart_silabs_dma_rx_flush()
449 dma_stop(data->dma_rx.dma_dev, data->dma_rx.dma_channel); in uart_silabs_dma_rx_cb()
462 dma_stop(data->dma_tx.dma_dev, data->dma_tx.dma_channel); in uart_silabs_dma_tx_cb()
504 ret = dma_config(data->dma_tx.dma_dev, data->dma_tx.dma_channel, &data->dma_tx.dma_cfg); in uart_silabs_async_tx()
510 ret = dma_start(data->dma_tx.dma_dev, data->dma_tx.dma_channel); in uart_silabs_async_tx()
537 if (!dma_get_status(data->dma_tx.dma_dev, data->dma_tx.dma_channel, &stat)) { in uart_silabs_async_tx_abort()
541 dma_stop(data->dma_tx.dma_dev, data->dma_tx.dma_channel); in uart_silabs_async_tx_abort()
583 ret = dma_config(data->dma_rx.dma_dev, data->dma_rx.dma_channel, &data->dma_rx.dma_cfg); in uart_silabs_async_rx_enable()
590 if (dma_start(data->dma_rx.dma_dev, data->dma_rx.dma_channel)) { in uart_silabs_async_rx_enable()
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| D | uart_ns16550.c | 293 uint8_t dma_channel; member
306 uint8_t dma_channel; member
1303 if (dma_status & BIT(dev_data->async.rx_dma_params.dma_channel)) {
1307 BIT(dev_data->async.rx_dma_params.dma_channel));
1500 dma_params->dma_channel,
1537 dma_params->dma_channel);
1574 if (channel == tx_params->dma_channel) {
1576 } else if (channel == rx_params->dma_channel) {
1590 dma_reload(dev, rx_params->dma_channel, data->phys_addr,
1592 dma_start(dev, rx_params->dma_channel);
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| D | uart_stm32.h | 65 uint32_t dma_channel; member
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| D | uart_stm32.c | 1234 if (dma_get_status(data->dma_rx.dma_dev, data->dma_rx.dma_channel, &stat) == 0) { in uart_stm32_dma_rx_flush()
1462 dma_stop(data->dma_rx.dma_dev, data->dma_rx.dma_channel); in uart_stm32_async_rx_disable()
1499 data->dma_tx.dma_channel, &stat)) { in uart_stm32_dma_tx_cb()
1528 dma_reload(data->dma_rx.dma_dev, data->dma_rx.dma_channel, in uart_stm32_dma_replace_buffer()
1533 dma_start(data->dma_rx.dma_dev, data->dma_rx.dma_channel); in uart_stm32_dma_replace_buffer()
1622 ret = dma_config(data->dma_tx.dma_dev, data->dma_tx.dma_channel, in uart_stm32_async_tx()
1630 if (dma_start(data->dma_tx.dma_dev, data->dma_tx.dma_channel)) { in uart_stm32_async_tx()
1686 ret = dma_config(data->dma_rx.dma_dev, data->dma_rx.dma_channel, in uart_stm32_async_rx_enable()
1694 if (dma_start(data->dma_rx.dma_dev, data->dma_rx.dma_channel)) { in uart_stm32_async_rx_enable()
1737 data->dma_tx.dma_channel, &stat)) { in uart_stm32_async_tx_abort()
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| /Zephyr-latest/drivers/adc/ |
| D | adc_mcux_adc16.c | 52 uint32_t dma_channel; member
214 dma_stop(data->dev_dma, data->adc_dma_config.dma_channel); in start_read()
268 dma_start(data->dev_dma, data->adc_dma_config.dma_channel); in mcux_adc16_start_channel()
287 dma_config(data->dev_dma, data->adc_dma_config.dma_channel, in adc_context_start_sampling()
412 data->adc_dma_config.dma_channel = in mcux_adc16_init()
417 data->adc_dma_config.dma_channel = in mcux_adc16_init()
420 if (data->adc_dma_config.dma_channel == -EINVAL) { in mcux_adc16_init()
424 LOG_DBG("dma allocated channel %d", data->adc_dma_config.dma_channel); in mcux_adc16_init()
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| D | adc_stm32wb0.c | 153 uint32_t dma_channel; member
737 err = dma_config(config->dmac, config->dma_channel, &data->dmac_config); in schedule_and_start_adc_sequence()
744 err = dma_start(config->dmac, config->dma_channel); in schedule_and_start_adc_sequence()
843 uint32_t dma_channel, int dma_status) in adc_stm32wb0_dma_callback() argument
854 if (dma_channel == config->dma_channel) { in adc_stm32wb0_dma_callback()
860 err = dma_stop(config->dmac, config->dma_channel); in adc_stm32wb0_dma_callback()
871 err = dma_stop(config->dmac, config->dma_channel); in adc_stm32wb0_dma_callback()
879 dma_channel, config->dma_channel); in adc_stm32wb0_dma_callback()
1203 .dma_channel = DT_DMAS_CELL_BY_IDX(ADC_NODE, 0, channel),
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| D | adc_esp32.c | 58 uint8_t dma_channel; member
173 err = dma_get_status(conf->dma_dev, conf->dma_channel, &dma_status); in adc_esp32_dma_start()
176 (unsigned int)conf->dma_channel, err); in adc_esp32_dma_start()
181 LOG_ERR("dma channel[%u] is busy!", (unsigned int)conf->dma_channel); in adc_esp32_dma_start()
196 err = dma_config(conf->dma_dev, conf->dma_channel, &dma_cfg); in adc_esp32_dma_start()
202 err = dma_start(conf->dma_dev, conf->dma_channel); in adc_esp32_dma_start()
219 err = dma_stop(conf->dma_dev, conf->dma_channel); in adc_esp32_dma_stop()
318 .dma_chan = conf->dma_channel, in adc_esp32_digi_start()
745 .dma_channel = COND_CODE_1(DT_INST_NODE_HAS_PROP(n, dmas), \
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| /Zephyr-latest/drivers/i2c/ |
| D | i2c_sam0.c | 50 uint8_t dma_channel; member
106 if (cfg->dma_channel != 0xFF) { in i2c_sam0_terminate_on_error()
107 dma_stop(cfg->dma_dev, cfg->dma_channel); in i2c_sam0_terminate_on_error()
268 if (cfg->dma_channel == 0xFF) { in i2c_sam0_dma_write_start()
296 retval = dma_config(cfg->dma_dev, cfg->dma_channel, &dma_cfg); in i2c_sam0_dma_write_start()
303 retval = dma_start(cfg->dma_dev, cfg->dma_channel); in i2c_sam0_dma_write_start()
360 if (cfg->dma_channel == 0xFF) { in i2c_sam0_dma_read_start()
389 retval = dma_config(cfg->dma_dev, cfg->dma_channel, &dma_cfg); in i2c_sam0_dma_read_start()
396 retval = dma_start(cfg->dma_dev, cfg->dma_channel); in i2c_sam0_dma_read_start()
784 .dma_channel = ATMEL_SAM0_DT_INST_DMA_CHANNEL(n, rx),
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| /Zephyr-latest/drivers/i3c/ |
| D | i3c_stm32.c | 79 uint32_t dma_channel; member
1096 ret = dma_config(data->dma_tc.dma_dev, data->dma_tc.dma_channel, &data->dma_tc.dma_cfg); in i3c_stm32_dma_msg_control_fifo_config()
1103 if (dma_start(data->dma_tc.dma_dev, data->dma_tc.dma_channel)) { in i3c_stm32_dma_msg_control_fifo_config()
1119 ret = dma_config(data->dma_rs.dma_dev, data->dma_rs.dma_channel, &data->dma_rs.dma_cfg); in i3c_stm32_dma_msg_status_fifo_config()
1126 if (dma_start(data->dma_rs.dma_dev, data->dma_rs.dma_channel)) { in i3c_stm32_dma_msg_status_fifo_config()
1151 ret = dma_config(dma_stream->dma_dev, dma_stream->dma_channel, &dma_stream->dma_cfg); in i3c_stm32_dma_msg_config()
1158 if (dma_start(dma_stream->dma_dev, dma_stream->dma_channel)) { in i3c_stm32_dma_msg_config()
2115 .dma_channel = DT_INST_DMAS_CELL_BY_NAME(index, dir, channel), \
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