| /Zephyr-latest/dts/xtensa/intel/ |
| D | intel_adsp_cavs.dtsi | 11 lpgpdma0: dma@7c000 {
13 #dma-cells = <1>;
18 dma-buf-size-alignment = <4>;
19 dma-copy-alignment = <4>;
24 lpgpdma1: dma@7d000 {
26 #dma-cells = <1>;
31 dma-buf-size-alignment = <4>;
32 dma-copy-alignment = <4>;
37 hda_link_out: dma@72400 {
39 #dma-cells = <1>;
[all …]
|
| /Zephyr-latest/drivers/dma/ |
| D | Kconfig | 26 module-str = dma
29 source "drivers/dma/Kconfig.stm32"
31 source "drivers/dma/Kconfig.sam_xdmac"
33 source "drivers/dma/Kconfig.dw"
35 source "drivers/dma/Kconfig.nios2_msgdma"
37 source "drivers/dma/Kconfig.sam0"
39 source "drivers/dma/Kconfig.mcux_edma"
41 source "drivers/dma/Kconfig.mcux_lpc"
43 source "drivers/dma/Kconfig.dma_pl330"
45 source "drivers/dma/Kconfig.iproc_pax"
[all …]
|
| D | dma_stm32_v1.c | 238 void stm32_dma_dump_stream_irq(DMA_TypeDef *dma, uint32_t id) in stm32_dma_dump_stream_irq() argument
241 dma_stm32_is_tc_active(dma, id), in stm32_dma_dump_stream_irq()
242 dma_stm32_is_ht_active(dma, id), in stm32_dma_dump_stream_irq()
243 dma_stm32_is_te_active(dma, id), in stm32_dma_dump_stream_irq()
244 dma_stm32_is_dme_active(dma, id), in stm32_dma_dump_stream_irq()
245 dma_stm32_is_fe_active(dma, id)); in stm32_dma_dump_stream_irq()
248 inline bool stm32_dma_is_tc_irq_active(DMA_TypeDef *dma, uint32_t id) in stm32_dma_is_tc_irq_active() argument
250 return LL_DMA_IsEnabledIT_TC(dma, dma_stm32_id_to_stream(id)) && in stm32_dma_is_tc_irq_active()
251 dma_stm32_is_tc_active(dma, id); in stm32_dma_is_tc_irq_active()
254 inline bool stm32_dma_is_ht_irq_active(DMA_TypeDef *dma, uint32_t id) in stm32_dma_is_ht_irq_active() argument
[all …]
|
| D | dma_stm32u5.c | 49 DMA_TypeDef *dma = (DMA_TypeDef *)(config->base); in dma_stm32_dump_stream_irq() local
51 stm32_dma_dump_stream_irq(dma, id); in dma_stm32_dump_stream_irq()
57 DMA_TypeDef *dma = (DMA_TypeDef *)(config->base); in dma_stm32_clear_stream_irq() local
59 dma_stm32_clear_tc(dma, id); in dma_stm32_clear_stream_irq()
60 dma_stm32_clear_ht(dma, id); in dma_stm32_clear_stream_irq()
61 stm32_dma_clear_stream_irq(dma, id); in dma_stm32_clear_stream_irq()
102 static inline bool dma_stm32_is_dte_active(DMA_TypeDef *dma, uint32_t id) in dma_stm32_is_dte_active() argument
104 return LL_DMA_IsActiveFlag_DTE(dma, dma_stm32_id_to_stream(id)); in dma_stm32_is_dte_active()
108 static inline bool dma_stm32_is_ule_active(DMA_TypeDef *dma, uint32_t id) in dma_stm32_is_ule_active() argument
110 return LL_DMA_IsActiveFlag_ULE(dma, dma_stm32_id_to_stream(id)); in dma_stm32_is_ule_active()
[all …]
|
| D | dma_stm32_v2.c | 253 void stm32_dma_dump_stream_irq(DMA_TypeDef *dma, uint32_t id) in stm32_dma_dump_stream_irq() argument
256 dma_stm32_is_tc_active(dma, id), in stm32_dma_dump_stream_irq()
257 dma_stm32_is_ht_active(dma, id), in stm32_dma_dump_stream_irq()
258 dma_stm32_is_te_active(dma, id), in stm32_dma_dump_stream_irq()
259 dma_stm32_is_gi_active(dma, id)); in stm32_dma_dump_stream_irq()
262 bool stm32_dma_is_tc_irq_active(DMA_TypeDef *dma, uint32_t id) in stm32_dma_is_tc_irq_active() argument
264 return LL_DMA_IsEnabledIT_TC(dma, dma_stm32_id_to_stream(id)) && in stm32_dma_is_tc_irq_active()
265 dma_stm32_is_tc_active(dma, id); in stm32_dma_is_tc_irq_active()
268 bool stm32_dma_is_ht_irq_active(DMA_TypeDef *dma, uint32_t id) in stm32_dma_is_ht_irq_active() argument
270 return LL_DMA_IsEnabledIT_HT(dma, dma_stm32_id_to_stream(id)) && in stm32_dma_is_ht_irq_active()
[all …]
|
| D | dma_xmc4xxx.c | 69 XMC_DMA_t *dma; member
81 uint32_t channels_event = get_channels_event(dma); \
89 XMC_DMA_CH_ClearEventStatus(dma, channel, XMC_DMA_CH_##event_test); \
103 XMC_DMA_t *dma = dev_cfg->dma; in dma_xmc4xxx_isr() local
113 event = XMC_DMA_GetEventStatus(dma); in dma_xmc4xxx_isr()
204 XMC_DMA_t *dma = dev_cfg->dma; in dma_xmc4xxx_config() local
238 if ((uint32_t)dma != (uint32_t)XMC_DMA0 || channel >= 2) { in dma_xmc4xxx_config()
274 if (XMC_DMA_CH_IsEnabled(dma, channel)) { in dma_xmc4xxx_config()
279 XMC_DMA_CH_ClearEventStatus(dma, channel, ALL_EVENTS); in dma_xmc4xxx_config()
285 dma->CH[channel].SAR = block->source_address; in dma_xmc4xxx_config()
[all …]
|
| D | dma_stm32.c | 73 DMA_TypeDef *dma = (DMA_TypeDef *)(config->base); in dma_stm32_dump_stream_irq() local
75 stm32_dma_dump_stream_irq(dma, id); in dma_stm32_dump_stream_irq()
81 DMA_TypeDef *dma = (DMA_TypeDef *)(config->base); in dma_stm32_clear_stream_irq() local
83 dma_stm32_clear_tc(dma, id); in dma_stm32_clear_stream_irq()
84 dma_stm32_clear_ht(dma, id); in dma_stm32_clear_stream_irq()
85 stm32_dma_clear_stream_irq(dma, id); in dma_stm32_clear_stream_irq()
91 DMA_TypeDef *dma = (DMA_TypeDef *)(config->base); in dma_stm32_irq_handler() local
115 if (stm32_dma_is_ht_irq_active(dma, id)) { in dma_stm32_irq_handler()
118 dma_stm32_clear_ht(dma, id); in dma_stm32_irq_handler()
121 } else if (stm32_dma_is_tc_irq_active(dma, id)) { in dma_stm32_irq_handler()
[all …]
|
| D | dma_stm32.h | 82 bool stm32_dma_is_irq_active(DMA_TypeDef *dma, uint32_t id);
83 bool stm32_dma_is_ht_irq_active(DMA_TypeDef *dma, uint32_t id);
84 bool stm32_dma_is_tc_irq_active(DMA_TypeDef *dma, uint32_t id);
86 void stm32_dma_dump_stream_irq(DMA_TypeDef *dma, uint32_t id);
87 void stm32_dma_clear_stream_irq(DMA_TypeDef *dma, uint32_t id);
88 bool stm32_dma_is_irq_happened(DMA_TypeDef *dma, uint32_t id);
89 bool stm32_dma_is_unexpected_irq_happened(DMA_TypeDef *dma, uint32_t id);
90 void stm32_dma_enable_stream(DMA_TypeDef *dma, uint32_t id);
91 bool stm32_dma_is_enabled_stream(DMA_TypeDef *dma, uint32_t id);
92 int stm32_dma_disable_stream(DMA_TypeDef *dma, uint32_t id);
[all …]
|
| D | dma_stm32_bdma.c | 220 void stm32_bdma_dump_channel_irq(BDMA_TypeDef *dma, uint32_t id) in stm32_bdma_dump_channel_irq() argument
223 bdma_stm32_is_te_active(dma, id), in stm32_bdma_dump_channel_irq()
224 bdma_stm32_is_ht_active(dma, id), in stm32_bdma_dump_channel_irq()
225 bdma_stm32_is_tc_active(dma, id), in stm32_bdma_dump_channel_irq()
226 bdma_stm32_is_gi_active(dma, id)); in stm32_bdma_dump_channel_irq()
229 inline bool stm32_bdma_is_tc_irq_active(BDMA_TypeDef *dma, uint32_t id) in stm32_bdma_is_tc_irq_active() argument
231 return LL_BDMA_IsEnabledIT_TC(dma, bdma_stm32_id_to_channel(id)) && in stm32_bdma_is_tc_irq_active()
232 bdma_stm32_is_tc_active(dma, id); in stm32_bdma_is_tc_irq_active()
235 inline bool stm32_bdma_is_ht_irq_active(BDMA_TypeDef *dma, uint32_t id) in stm32_bdma_is_ht_irq_active() argument
237 return LL_BDMA_IsEnabledIT_HT(dma, bdma_stm32_id_to_channel(id)) && in stm32_bdma_is_ht_irq_active()
[all …]
|
| /Zephyr-latest/tests/drivers/dma/loop_transfer/src/ |
| D | test_dma_loop.c | 86 static int test_loop(const struct device *dma) in test_loop() argument
101 if (!device_is_ready(dma)) { in test_loop()
106 TC_PRINT("Preparing DMA Controller: %s\n", dma->name); in test_loop()
113 dma_cfg.user_data = (void *)dma; in test_loop()
125 chan_id = dma_request_channel(dma, NULL); in test_loop()
142 if (dma_config(dma, chan_id, &dma_cfg)) { in test_loop()
147 if (dma_start(dma, chan_id)) { in test_loop()
157 if (dma_stop(dma, chan_id)) { in test_loop()
172 TC_PRINT("Finished DMA: %s\n", dma->name); in test_loop()
176 static int test_loop_suspend_resume(const struct device *dma) in test_loop_suspend_resume() argument
[all …]
|
| /Zephyr-latest/tests/drivers/dma/chan_blen_transfer/src/ |
| D | test_dma.c | 35 static int test_task(const struct device *dma, uint32_t chan_id, uint32_t blen) in test_task() argument
40 if (!device_is_ready(dma)) { in test_task()
60 dma->name, chan_id, blen >> 3); in test_task()
73 if (dma_config(dma, chan_id, &dma_cfg)) { in test_task()
78 if (dma_start(dma, chan_id)) { in test_task()
98 const struct device *dma = DEVICE_DT_GET(DT_NODELABEL(dma_name)); \
99 zassert_true((test_task(dma, CONFIG_DMA_TRANSFER_CHANNEL_NR_0, 8) == TC_PASS)); \
104 const struct device *dma = DEVICE_DT_GET(DT_NODELABEL(dma_name)); \
105 zassert_true((test_task(dma, CONFIG_DMA_TRANSFER_CHANNEL_NR_1, 8) == TC_PASS)); \
110 const struct device *dma = DEVICE_DT_GET(DT_NODELABEL(dma_name)); \
[all …]
|
| /Zephyr-latest/dts/arm/st/g4/ |
| D | stm32g431.dtsi | 13 dma1: dma@40020000 {
15 dma-requests = <6>;
18 dma2: dma@40020400 {
20 dma-requests = <6>;
21 dma-offset = <6>;
25 dma-channels = <12>;
|
| /Zephyr-latest/tests/drivers/spi/spi_loopback/boards/ |
| D | rpi_pico_pl022_dma.overlay | 7 #include <zephyr/dt-bindings/dma/rpi-pico-dma-rp2040.h>
9 &dma {
16 dmas = <&dma 0 RPI_PICO_DMA_SLOT_SPI0_TX 0>, <&dma 1 RPI_PICO_DMA_SLOT_SPI0_RX 0>;
17 dma-names = "tx", "rx";
|
| /Zephyr-latest/tests/boards/silabs/dma/block_append/src/ |
| D | test_dma_ba.c | 53 const struct device *dma; in test_ba_restart_transfer() local
66 dma = DEVICE_DT_GET(DT_ALIAS(dma0)); in test_ba_restart_transfer()
67 if (!device_is_ready(dma)) { in test_ba_restart_transfer()
82 chan_id = dma_request_channel(dma, NULL); in test_ba_restart_transfer()
94 if (dma_config(dma, chan_id, &dma_cfg)) { in test_ba_restart_transfer()
101 if (dma_start(dma, chan_id)) { in test_ba_restart_transfer()
114 silabs_ldma_append_block(dma, chan_id, &dma_cfg); in test_ba_restart_transfer()
133 const struct device *dma; in test_ba_restart_in_isr() local
147 dma = DEVICE_DT_GET(DT_ALIAS(dma0)); in test_ba_restart_in_isr()
148 if (!device_is_ready(dma)) { in test_ba_restart_in_isr()
[all …]
|
| /Zephyr-latest/tests/drivers/dma/scatter_gather/boards/ |
| D | native_sim.overlay | 7 &dma {
8 dma-channels = <2>;
9 dma-requests = <4>;
13 test_dma0: &dma { };
|
| /Zephyr-latest/tests/drivers/dma/cyclic/src/ |
| D | test_dma_cyclic.c | 42 const struct device *dma; in test_cyclic() local
51 dma = DEVICE_DT_GET(DT_ALIAS(dma0)); in test_cyclic()
52 if (!device_is_ready(dma)) { in test_cyclic()
69 chan_id = dma_request_channel(dma, NULL); in test_cyclic()
83 if (dma_config(dma, chan_id, &dma_cfg)) { in test_cyclic()
91 if (dma_start(dma, chan_id)) { in test_cyclic()
101 if (dma_suspend(dma, chan_id) != 0) { in test_cyclic()
116 if (dma_resume(dma, chan_id) != 0) { in test_cyclic()
126 if (dma_stop(dma, chan_id) != 0) { in test_cyclic()
|
| /Zephyr-latest/drivers/spi/ |
| D | spi_gd32.c | 65 const struct spi_gd32_dma_config dma[NUM_OF_DIRECTION]; member
75 struct spi_gd32_dma_data dma[NUM_OF_DIRECTION]; member
88 if (cfg->dma[TX].dev && cfg->dma[RX].dev) { in spi_gd32_dma_enabled()
254 struct dma_config *dma_cfg = &data->dma[dir].config; in spi_gd32_dma_setup()
255 struct dma_block_config *block_cfg = &data->dma[dir].block; in spi_gd32_dma_setup()
256 const struct spi_gd32_dma_config *dma = &cfg->dma[dir]; in spi_gd32_dma_setup() local
268 dma_cfg->dma_slot = cfg->dma[dir].slot; in spi_gd32_dma_setup()
270 GD32_DMA_CONFIG_PRIORITY(cfg->dma[dir].config); in spi_gd32_dma_setup()
309 ret = dma_config(dma->dev, dma->channel, dma_cfg); in spi_gd32_dma_setup()
311 LOG_ERR("dma_config %p failed %d\n", dma->dev, ret); in spi_gd32_dma_setup()
[all …]
|
| /Zephyr-latest/tests/boards/intel_adsp/hda/src/ |
| D | dma.c | 46 const struct device *dma; in ZTEST() local
70 dma = DEVICE_DT_GET(DT_NODELABEL(hda_host_in)); in ZTEST()
71 zassert_true(device_is_ready(dma), "DMA device is not ready"); in ZTEST()
73 channel = dma_request_channel(dma, NULL); in ZTEST()
96 res = dma_config(dma, channel, &dma_cfg); in ZTEST()
100 res = dma_start(dma, channel); in ZTEST()
108 res = dma_reload(dma, channel, 0, 0, DMA_BUF_SIZE); in ZTEST()
116 res = dma_get_status(dma, channel, &status); in ZTEST()
138 res = dma_stop(dma, channel); in ZTEST()
147 const struct device *dma; in test_hda_host_out_dma() local
[all …]
|
| /Zephyr-latest/samples/drivers/i2s/echo/boards/ |
| D | esp32s3_devkitc_procpu.overlay | 38 dmas = <&dma 3>;
39 dma-names = "tx";
48 dmas = <&dma 4>;
49 dma-names = "rx";
52 &dma {
|
| /Zephyr-latest/tests/drivers/uart/uart_async_api/boards/ |
| D | esp32c3_luatos_core.overlay | 25 dmas = <&dma 0>, <&dma 1>;
26 dma-names = "rx", "tx";
29 &dma {
|
| D | esp32s3_luatos_core_procpu.overlay | 24 dmas = <&dma 0>, <&dma 1>;
25 dma-names = "rx", "tx";
28 &dma {
|
| D | esp32s3_devkitm_procpu.overlay | 24 dmas = <&dma 0>, <&dma 1>;
25 dma-names = "rx", "tx";
28 &dma {
|
| D | ttgo_t8c3.overlay | 25 dmas = <&dma 0>, <&dma 1>;
26 dma-names = "rx", "tx";
29 &dma {
|
| /Zephyr-latest/tests/drivers/uart/uart_async_api/socs/ |
| D | esp32c3.overlay | 25 dmas = <&dma 0>, <&dma 1>;
26 dma-names = "rx", "tx";
29 &dma {
|
| D | esp32c3_usb.overlay | 25 dmas = <&dma 0>, <&dma 1>;
26 dma-names = "rx", "tx";
29 &dma {
|
