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Searched refs:blk_cfg (Results 1 – 22 of 22) sorted by relevance

/Zephyr-latest/drivers/spi/
Dspi_mcux_flexcomm.c390 struct dma_block_config *blk_cfg; in spi_mcux_dma_tx_load() local
400 blk_cfg = &stream->dma_blk_cfg[0]; in spi_mcux_dma_tx_load()
403 memset(blk_cfg, 0, sizeof(struct dma_block_config)); in spi_mcux_dma_tx_load()
414 blk_cfg->source_address = (uint32_t)&data->dummy_tx_buffer; in spi_mcux_dma_tx_load()
415 blk_cfg->dest_address = (uint32_t)&base->FIFOWR; in spi_mcux_dma_tx_load()
416 blk_cfg->block_size = (word_size > 8) ? in spi_mcux_dma_tx_load()
418 blk_cfg->next_block = &stream->dma_blk_cfg[1]; in spi_mcux_dma_tx_load()
419 blk_cfg->source_addr_adj = DMA_ADDR_ADJ_NO_CHANGE; in spi_mcux_dma_tx_load()
420 blk_cfg->dest_addr_adj = DMA_ADDR_ADJ_NO_CHANGE; in spi_mcux_dma_tx_load()
422 blk_cfg = &stream->dma_blk_cfg[1]; in spi_mcux_dma_tx_load()
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Dspi_xmc4xxx.c54 struct dma_block_config blk_cfg; member
404 dma_rx->blk_cfg.dest_address = (uint32_t)ctx->rx_buf; in spi_xmc4xxx_transceive_dma()
405 dma_rx->blk_cfg.dest_addr_adj = DMA_ADDR_ADJ_INCREMENT; in spi_xmc4xxx_transceive_dma()
406 dma_rx->blk_cfg.block_size = dma_len; in spi_xmc4xxx_transceive_dma()
407 dma_rx->blk_cfg.source_addr_adj = DMA_ADDR_ADJ_NO_CHANGE; in spi_xmc4xxx_transceive_dma()
430 dma_tx->blk_cfg.source_address = (uint32_t)ctx->tx_buf; in spi_xmc4xxx_transceive_dma()
431 dma_tx->blk_cfg.source_addr_adj = DMA_ADDR_ADJ_INCREMENT; in spi_xmc4xxx_transceive_dma()
433 dma_tx->blk_cfg.source_address = (uint32_t)&tx_dummy_data; in spi_xmc4xxx_transceive_dma()
434 dma_tx->blk_cfg.source_addr_adj = DMA_ADDR_ADJ_NO_CHANGE; in spi_xmc4xxx_transceive_dma()
437 dma_tx->blk_cfg.block_size = dma_len; in spi_xmc4xxx_transceive_dma()
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Dspi_ll_stm32.c161 struct dma_block_config *blk_cfg; in spi_stm32_dma_tx_load() local
167 blk_cfg = &stream->dma_blk_cfg; in spi_stm32_dma_tx_load()
170 memset(blk_cfg, 0, sizeof(struct dma_block_config)); in spi_stm32_dma_tx_load()
171 blk_cfg->block_size = len; in spi_stm32_dma_tx_load()
180 blk_cfg->source_address = (uint32_t)&dummy_rx_tx_buffer; in spi_stm32_dma_tx_load()
181 blk_cfg->source_addr_adj = DMA_ADDR_ADJ_NO_CHANGE; in spi_stm32_dma_tx_load()
183 blk_cfg->source_address = (uint32_t)buf; in spi_stm32_dma_tx_load()
185 blk_cfg->source_addr_adj = DMA_ADDR_ADJ_INCREMENT; in spi_stm32_dma_tx_load()
187 blk_cfg->source_addr_adj = DMA_ADDR_ADJ_NO_CHANGE; in spi_stm32_dma_tx_load()
191 blk_cfg->dest_address = ll_func_dma_get_reg_addr(cfg->spi, SPI_STM32_DMA_TX); in spi_stm32_dma_tx_load()
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Dspi_andes_atcspi200.c356 struct dma_block_config *blk_cfg = &data->dma_tx.dma_blk_cfg; in spi_dma_tx_load() local
365 blk_cfg->next_block = next_blk_cfg; in spi_dma_tx_load()
394 blk_cfg = next_blk_cfg; in spi_dma_tx_load()
471 struct dma_block_config *blk_cfg = &data->dma_rx.dma_blk_cfg; in spi_dma_rx_load() local
480 blk_cfg->next_block = next_blk_cfg; in spi_dma_rx_load()
508 blk_cfg = next_blk_cfg; in spi_dma_rx_load()
/Zephyr-latest/drivers/dma/
Ddma_intel_adsp_hda.c35 struct dma_block_config *blk_cfg; in intel_adsp_hda_dma_host_in_config() local
47 blk_cfg = dma_cfg->head_block; in intel_adsp_hda_dma_host_in_config()
48 buf = (uint8_t *)(uintptr_t)(blk_cfg->source_address); in intel_adsp_hda_dma_host_in_config()
50 blk_cfg->block_size); in intel_adsp_hda_dma_host_in_config()
54 blk_cfg->block_size & HDA_ALIGN_MASK; in intel_adsp_hda_dma_host_in_config()
69 struct dma_block_config *blk_cfg; in intel_adsp_hda_dma_host_out_config() local
81 blk_cfg = dma_cfg->head_block; in intel_adsp_hda_dma_host_out_config()
82 buf = (uint8_t *)(uintptr_t)(blk_cfg->dest_address); in intel_adsp_hda_dma_host_out_config()
85 blk_cfg->block_size); in intel_adsp_hda_dma_host_out_config()
89 blk_cfg->block_size & HDA_ALIGN_MASK; in intel_adsp_hda_dma_host_out_config()
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Ddma_dw_axi.c446 struct dma_block_config *blk_cfg; in dma_dw_axi_config() local
514 blk_cfg = cfg->head_block; in dma_dw_axi_config()
533 lli_desc->sar = blk_cfg->source_address; in dma_dw_axi_config()
534 lli_desc->dar = blk_cfg->dest_address; in dma_dw_axi_config()
537 lli_desc->block_ts_lo = (blk_cfg->block_size / cfg->source_data_size) - 1; in dma_dw_axi_config()
599 blk_cfg = blk_cfg->next_block; in dma_dw_axi_config()
/Zephyr-latest/drivers/spi/spi_nxp_lpspi/
Dspi_nxp_lpspi_dma.c37 struct dma_block_config *blk_cfg = &stream->dma_blk_cfg; in spi_mcux_dma_common_load() local
39 memset(blk_cfg, 0, sizeof(struct dma_block_config)); in spi_mcux_dma_common_load()
41 blk_cfg->block_size = len; in spi_mcux_dma_common_load()
45 stream->dma_cfg.head_block = blk_cfg; in spi_mcux_dma_common_load()
47 return blk_cfg; in spi_mcux_dma_common_load()
56 struct dma_block_config *blk_cfg = spi_mcux_dma_common_load(stream, dev, buf, len); in spi_mcux_dma_tx_load() local
60 blk_cfg->source_address = (uint32_t)&tx_nop_val; in spi_mcux_dma_tx_load()
63 blk_cfg->source_address = (uint32_t)buf; in spi_mcux_dma_tx_load()
68 blk_cfg->dest_address = LPSPI_GetTxRegisterAddress(base); in spi_mcux_dma_tx_load()
79 struct dma_block_config *blk_cfg = spi_mcux_dma_common_load(stream, dev, buf, len); in spi_mcux_dma_rx_load() local
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/Zephyr-latest/subsys/mgmt/ec_host_cmd/backends/
Dec_host_cmd_backend_spi_stm32.c446 struct dma_block_config *blk_cfg; in spi_config_dma_tx() local
450 blk_cfg = &stream->dma_blk_cfg; in spi_config_dma_tx()
453 memset(blk_cfg, 0, sizeof(struct dma_block_config)); in spi_config_dma_tx()
454 blk_cfg->block_size = 0; in spi_config_dma_tx()
457 blk_cfg->dest_address = dma_dest_addr(spi); in spi_config_dma_tx()
458 blk_cfg->dest_addr_adj = DMA_ADDR_ADJ_NO_CHANGE; in spi_config_dma_tx()
460 blk_cfg->source_address = (uint32_t)hc_spi->tx_buf; in spi_config_dma_tx()
461 blk_cfg->source_addr_adj = DMA_ADDR_ADJ_INCREMENT; in spi_config_dma_tx()
463 blk_cfg->fifo_mode_control = hc_spi->dma_tx->fifo_threshold; in spi_config_dma_tx()
465 stream->dma_cfg.head_block = blk_cfg; in spi_config_dma_tx()
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/Zephyr-latest/drivers/audio/
Ddmic_mcux.c277 struct dma_block_config blk_cfg[CONFIG_DMIC_MCUX_DMA_BUFFERS] = {0}; in dmic_mcux_setup_dma() local
293 dma_cfg.head_block = &blk_cfg[0]; in dmic_mcux_setup_dma()
308 blk_cfg[blk].source_address = in dmic_mcux_setup_dma()
318 blk_cfg[blk].dest_address = in dmic_mcux_setup_dma()
320 blk_cfg[blk].dest_scatter_interval = in dmic_mcux_setup_dma()
322 blk_cfg[blk].dest_scatter_en = 1; in dmic_mcux_setup_dma()
323 blk_cfg[blk].source_addr_adj = DMA_ADDR_ADJ_NO_CHANGE; in dmic_mcux_setup_dma()
324 blk_cfg[blk].dest_addr_adj = DMA_ADDR_ADJ_INCREMENT; in dmic_mcux_setup_dma()
325 blk_cfg[blk].block_size = dma_buf_size; in dmic_mcux_setup_dma()
330 blk_cfg[blk].source_reload_en = 1; in dmic_mcux_setup_dma()
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/Zephyr-latest/drivers/mipi_dbi/
Dmipi_dbi_nxp_lcdic.c94 struct dma_block_config blk_cfg[2]; member
175 stream->dma_cfg.head_block = &stream->blk_cfg[0]; in mipi_dbi_lcdic_start_dma()
179 stream->blk_cfg[0].source_address = (uint32_t)&data->unaligned_word; in mipi_dbi_lcdic_start_dma()
180 stream->blk_cfg[0].dest_address = (uint32_t)&config->base->TFIFO_WDATA; in mipi_dbi_lcdic_start_dma()
182 stream->blk_cfg[0].block_size = sizeof(uint32_t); in mipi_dbi_lcdic_start_dma()
184 stream->blk_cfg[0].next_block = NULL; in mipi_dbi_lcdic_start_dma()
187 stream->blk_cfg[0].source_address = (uint32_t)data->xfer_buf; in mipi_dbi_lcdic_start_dma()
188 stream->blk_cfg[0].dest_address = (uint32_t)&config->base->TFIFO_WDATA; in mipi_dbi_lcdic_start_dma()
190 stream->blk_cfg[0].block_size = aligned_len; in mipi_dbi_lcdic_start_dma()
194 stream->blk_cfg[0].next_block = in mipi_dbi_lcdic_start_dma()
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Dmipi_dbi_nxp_flexio_lcdif.c238 struct dma_block_config *blk_cfg; in mipi_dbi_flexio_ldcif_write_display() local
252 blk_cfg = &stream->dma_blk_cfg; in mipi_dbi_flexio_ldcif_write_display()
258 memset(blk_cfg, 0, sizeof(struct dma_block_config)); in mipi_dbi_flexio_ldcif_write_display()
261 blk_cfg->source_address = (uint32_t)framebuf; in mipi_dbi_flexio_ldcif_write_display()
264 blk_cfg->dest_address = FLEXIO_MCULCD_GetTxDataRegisterAddress(flexio_lcd); in mipi_dbi_flexio_ldcif_write_display()
265 blk_cfg->block_size = desc->buf_size; in mipi_dbi_flexio_ldcif_write_display()
/Zephyr-latest/drivers/i2s/
Di2s_mcux_flexcomm.c411 struct dma_block_config *blk_cfg; in i2s_mcux_config_dma_blocks() local
416 blk_cfg = &dev_data->rx_dma_blocks[0]; in i2s_mcux_config_dma_blocks()
417 memset(blk_cfg, 0, sizeof(dev_data->rx_dma_blocks)); in i2s_mcux_config_dma_blocks()
420 blk_cfg = &dev_data->tx_dma_block; in i2s_mcux_config_dma_blocks()
421 memset(blk_cfg, 0, sizeof(dev_data->tx_dma_block)); in i2s_mcux_config_dma_blocks()
424 stream->dma_cfg.head_block = blk_cfg; in i2s_mcux_config_dma_blocks()
428 blk_cfg->source_address = (uint32_t)&base->FIFORD; in i2s_mcux_config_dma_blocks()
429 blk_cfg->dest_address = (uint32_t)buffer[0]; in i2s_mcux_config_dma_blocks()
430 blk_cfg->block_size = block_size; in i2s_mcux_config_dma_blocks()
431 blk_cfg->next_block = &dev_data->rx_dma_blocks[1]; in i2s_mcux_config_dma_blocks()
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Di2s_ll_stm32.c474 struct dma_block_config blk_cfg; in start_dma() local
477 memset(&blk_cfg, 0, sizeof(blk_cfg)); in start_dma()
478 blk_cfg.block_size = blk_size; in start_dma()
479 blk_cfg.source_address = (uint32_t)src; in start_dma()
480 blk_cfg.dest_address = (uint32_t)dst; in start_dma()
482 blk_cfg.source_addr_adj = DMA_ADDR_ADJ_INCREMENT; in start_dma()
484 blk_cfg.source_addr_adj = DMA_ADDR_ADJ_NO_CHANGE; in start_dma()
487 blk_cfg.dest_addr_adj = DMA_ADDR_ADJ_INCREMENT; in start_dma()
489 blk_cfg.dest_addr_adj = DMA_ADDR_ADJ_NO_CHANGE; in start_dma()
491 blk_cfg.fifo_mode_control = fifo_threshold; in start_dma()
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Di2s_mcux_sai.c698 struct dma_block_config *blk_cfg = &strm->dma_block; in i2s_tx_stream_start() local
700 memset(blk_cfg, 0, sizeof(struct dma_block_config)); in i2s_tx_stream_start()
704 blk_cfg->dest_address = (uint32_t)&base->TDR[data_path]; in i2s_tx_stream_start()
705 blk_cfg->source_address = (uint32_t)buffer; in i2s_tx_stream_start()
706 blk_cfg->block_size = strm->cfg.block_size; in i2s_tx_stream_start()
707 blk_cfg->dest_scatter_en = 1; in i2s_tx_stream_start()
779 struct dma_block_config *blk_cfg = &strm->dma_block; in i2s_rx_stream_start() local
781 memset(blk_cfg, 0, sizeof(struct dma_block_config)); in i2s_rx_stream_start()
785 blk_cfg->dest_address = (uint32_t)buffer; in i2s_rx_stream_start()
786 blk_cfg->source_address = (uint32_t)&base->RDR[data_path]; in i2s_rx_stream_start()
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Di2s_sam_ssc.c184 struct dma_block_config blk_cfg; in start_dma() local
187 (void)memset(&blk_cfg, 0, sizeof(blk_cfg)); in start_dma()
188 blk_cfg.block_size = blk_size; in start_dma()
189 blk_cfg.source_address = (uint32_t)src; in start_dma()
190 blk_cfg.dest_address = (uint32_t)dst; in start_dma()
192 cfg->head_block = &blk_cfg; in start_dma()
/Zephyr-latest/drivers/serial/
Duart_silabs_usart.c34 struct dma_block_config blk_cfg; member
494 data->dma_tx.blk_cfg.source_address = (uint32_t)data->dma_tx.buffer; in uart_silabs_async_tx()
495 data->dma_tx.blk_cfg.block_size = data->dma_tx.buffer_length; in uart_silabs_async_tx()
580 data->dma_rx.blk_cfg.block_size = buf_size; in uart_silabs_async_rx_enable()
581 data->dma_rx.blk_cfg.dest_address = (uint32_t)data->dma_rx.buffer; in uart_silabs_async_rx_enable()
670 data->dma_rx.blk_cfg.dest_address = (uint32_t)buf; in uart_silabs_async_rx_buf_rsp()
671 data->dma_rx.blk_cfg.block_size = len; in uart_silabs_async_rx_buf_rsp()
710 memset(&data->dma_rx.blk_cfg, 0, sizeof(data->dma_rx.blk_cfg)); in uart_silabs_async_init()
711 data->dma_rx.blk_cfg.source_address = (uintptr_t)&(usart->RXDATA); in uart_silabs_async_init()
712 data->dma_rx.blk_cfg.dest_address = 0; in uart_silabs_async_init()
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Duart_stm32.c1523 data->dma_rx.blk_cfg.block_size = data->dma_rx.buffer_length; in uart_stm32_dma_replace_buffer()
1524 data->dma_rx.blk_cfg.dest_address = (uint32_t)data->dma_rx.buffer; in uart_stm32_dma_replace_buffer()
1529 data->dma_rx.blk_cfg.source_address, in uart_stm32_dma_replace_buffer()
1530 data->dma_rx.blk_cfg.dest_address, in uart_stm32_dma_replace_buffer()
1531 data->dma_rx.blk_cfg.block_size); in uart_stm32_dma_replace_buffer()
1619 data->dma_tx.blk_cfg.source_address = (uint32_t)data->dma_tx.buffer; in uart_stm32_async_tx()
1620 data->dma_tx.blk_cfg.block_size = data->dma_tx.buffer_length; in uart_stm32_async_tx()
1683 data->dma_rx.blk_cfg.block_size = buf_size; in uart_stm32_async_rx_enable()
1684 data->dma_rx.blk_cfg.dest_address = (uint32_t)data->dma_rx.buffer; in uart_stm32_async_rx_enable()
1843 memset(&data->dma_rx.blk_cfg, 0, sizeof(data->dma_rx.blk_cfg)); in uart_stm32_async_init()
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Duart_xmc4xxx.c44 struct dma_block_config blk_cfg; member
589 data->dma_rx.blk_cfg.source_address = (uint32_t)&config->uart->OUTR; in uart_xmc4xxx_async_init()
591 data->dma_rx.blk_cfg.source_address = (uint32_t)&config->uart->RBUF; in uart_xmc4xxx_async_init()
594 data->dma_rx.blk_cfg.source_addr_adj = DMA_ADDR_ADJ_NO_CHANGE; in uart_xmc4xxx_async_init()
595 data->dma_rx.blk_cfg.dest_addr_adj = DMA_ADDR_ADJ_INCREMENT; in uart_xmc4xxx_async_init()
596 data->dma_rx.dma_cfg.head_block = &data->dma_rx.blk_cfg; in uart_xmc4xxx_async_init()
608 data->dma_tx.blk_cfg.dest_address = (uint32_t)&config->uart->IN[0]; in uart_xmc4xxx_async_init()
610 data->dma_tx.blk_cfg.dest_address = (uint32_t)&config->uart->TBUF[0]; in uart_xmc4xxx_async_init()
613 data->dma_tx.blk_cfg.source_addr_adj = DMA_ADDR_ADJ_INCREMENT; in uart_xmc4xxx_async_init()
614 data->dma_tx.blk_cfg.dest_addr_adj = DMA_ADDR_ADJ_NO_CHANGE; in uart_xmc4xxx_async_init()
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Duart_ifx_cat1.c37 struct dma_block_config blk_cfg; member
502 dma_stream->blk_cfg.block_size = dma_stream->buf_len; in ifx_cat1_uart_async_dma_config_buffer()
505 dma_stream->blk_cfg.source_address = (uint32_t)dma_stream->buf; in ifx_cat1_uart_async_dma_config_buffer()
507 dma_stream->blk_cfg.dest_address = (uint32_t)dma_stream->buf; in ifx_cat1_uart_async_dma_config_buffer()
539 data->async.dma_tx.blk_cfg.block_size = 0; in ifx_cat1_uart_async_tx()
740 data->async.dma_rx.blk_cfg.block_size = 0; in ifx_cat1_uart_async_rx_enable()
790 data->async.dma_rx.blk_cfg.block_size = 0; in dma_callback_rx_rdy()
984 data->async.dma_rx.blk_cfg.source_address = in ifx_cat1_uart_init()
986 data->async.dma_rx.blk_cfg.source_addr_adj = DMA_ADDR_ADJ_NO_CHANGE; in ifx_cat1_uart_init()
987 data->async.dma_rx.blk_cfg.dest_addr_adj = DMA_ADDR_ADJ_INCREMENT; in ifx_cat1_uart_init()
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Duart_stm32.h71 struct dma_block_config blk_cfg; member
/Zephyr-latest/drivers/i3c/
Di3c_stm32.c85 struct dma_block_config blk_cfg; member
1093 data->dma_tc.blk_cfg.source_address = (uint32_t)data->control_fifo; in i3c_stm32_dma_msg_control_fifo_config()
1094 data->dma_tc.blk_cfg.block_size = data->fifo_len; in i3c_stm32_dma_msg_control_fifo_config()
1116 data->dma_rs.blk_cfg.dest_address = (uint32_t)data->status_fifo; in i3c_stm32_dma_msg_status_fifo_config()
1117 data->dma_rs.blk_cfg.block_size = data->fifo_len; in i3c_stm32_dma_msg_status_fifo_config()
1142 dma_stream->blk_cfg.dest_address = buf_addr; in i3c_stm32_dma_msg_config()
1145 dma_stream->blk_cfg.source_address = buf_addr; in i3c_stm32_dma_msg_config()
1150 dma_stream->blk_cfg.block_size = buf_len; in i3c_stm32_dma_msg_config()
1398 memset(&dma_stream->blk_cfg, 0, sizeof(dma_stream->blk_cfg)); in i3c_stm32_dma_stream_config()
1400 dma_stream->blk_cfg.source_address = src_addr; in i3c_stm32_dma_stream_config()
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/Zephyr-latest/drivers/adc/
Dadc_stm32.c225 struct dma_block_config *blk_cfg; in adc_stm32_dma_start() local
230 blk_cfg = &dma->dma_blk_cfg; in adc_stm32_dma_start()
233 blk_cfg->block_size = channel_count * sizeof(adc_data_size_t); in adc_stm32_dma_start()
236 blk_cfg->source_address = (uint32_t)LL_ADC_DMA_GetRegAddr(adc, LL_ADC_DMA_REG_REGULAR_DATA); in adc_stm32_dma_start()
237 blk_cfg->source_addr_adj = DMA_ADDR_ADJ_NO_CHANGE; in adc_stm32_dma_start()
238 blk_cfg->source_reload_en = 0; in adc_stm32_dma_start()
240 blk_cfg->dest_address = (uint32_t)buffer; in adc_stm32_dma_start()
241 blk_cfg->dest_addr_adj = DMA_ADDR_ADJ_INCREMENT; in adc_stm32_dma_start()
242 blk_cfg->dest_reload_en = 0; in adc_stm32_dma_start()
247 blk_cfg->fifo_mode_control = 0; in adc_stm32_dma_start()
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