1489 	data->dma_rx.blk_cfg.block_size = data->dma_rx.buffer_length;  in uart_stm32_dma_replace_buffer()
1490 	data->dma_rx.blk_cfg.dest_address = (uint32_t)data->dma_rx.buffer;  in uart_stm32_dma_replace_buffer()
1495 			data->dma_rx.blk_cfg.source_address,  in uart_stm32_dma_replace_buffer()
1496 			data->dma_rx.blk_cfg.dest_address,  in uart_stm32_dma_replace_buffer()
1497 			data->dma_rx.blk_cfg.block_size);  in uart_stm32_dma_replace_buffer()
1580 	data->dma_tx.blk_cfg.source_address = (uint32_t)data->dma_tx.buffer;  in uart_stm32_async_tx()
1581 	data->dma_tx.blk_cfg.block_size = data->dma_tx.buffer_length;  in uart_stm32_async_tx()
1644 	data->dma_rx.blk_cfg.block_size = buf_size;  in uart_stm32_async_rx_enable()
1645 	data->dma_rx.blk_cfg.dest_address = (uint32_t)data->dma_rx.buffer;  in uart_stm32_async_rx_enable()
1804 	memset(&data->dma_rx.blk_cfg, 0, sizeof(data->dma_rx.blk_cfg));  in uart_stm32_async_init()
1810 	data->dma_rx.blk_cfg.source_address =  in uart_stm32_async_init()
1813 	data->dma_rx.blk_cfg.source_address =  in uart_stm32_async_init()
1818 	data->dma_rx.blk_cfg.dest_address = 0; /* dest not ready */  in uart_stm32_async_init()
1821 		data->dma_rx.blk_cfg.source_addr_adj = DMA_ADDR_ADJ_INCREMENT;  in uart_stm32_async_init()
1823 		data->dma_rx.blk_cfg.source_addr_adj = DMA_ADDR_ADJ_NO_CHANGE;  in uart_stm32_async_init()
1827 		data->dma_rx.blk_cfg.dest_addr_adj = DMA_ADDR_ADJ_INCREMENT;  in uart_stm32_async_init()
1829 		data->dma_rx.blk_cfg.dest_addr_adj = DMA_ADDR_ADJ_NO_CHANGE;  in uart_stm32_async_init()
1833 	data->dma_rx.blk_cfg.source_reload_en  = 0;  in uart_stm32_async_init()
1834 	data->dma_rx.blk_cfg.dest_reload_en = 0;  in uart_stm32_async_init()
1835 	data->dma_rx.blk_cfg.fifo_mode_control = data->dma_rx.fifo_threshold;  in uart_stm32_async_init()
1837 	data->dma_rx.dma_cfg.head_block = &data->dma_rx.blk_cfg;  in uart_stm32_async_init()
1843 	memset(&data->dma_tx.blk_cfg, 0, sizeof(data->dma_tx.blk_cfg));  in uart_stm32_async_init()
1849 	data->dma_tx.blk_cfg.dest_address =  in uart_stm32_async_init()
1852 	data->dma_tx.blk_cfg.dest_address =  in uart_stm32_async_init()
1857 	data->dma_tx.blk_cfg.source_address = 0; /* not ready */  in uart_stm32_async_init()
1860 		data->dma_tx.blk_cfg.source_addr_adj = DMA_ADDR_ADJ_INCREMENT;  in uart_stm32_async_init()
1862 		data->dma_tx.blk_cfg.source_addr_adj = DMA_ADDR_ADJ_NO_CHANGE;  in uart_stm32_async_init()
1866 		data->dma_tx.blk_cfg.dest_addr_adj = DMA_ADDR_ADJ_INCREMENT;  in uart_stm32_async_init()
1868 		data->dma_tx.blk_cfg.dest_addr_adj = DMA_ADDR_ADJ_NO_CHANGE;  in uart_stm32_async_init()
1871 	data->dma_tx.blk_cfg.fifo_mode_control = data->dma_tx.fifo_threshold;  in uart_stm32_async_init()
1873 	data->dma_tx.dma_cfg.head_block = &data->dma_tx.blk_cfg;  in uart_stm32_async_init()