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/Zephyr-Core-2.7.6/tests/kernel/common/src/
Dbitfield.c14 #define BIT_INDEX(bit) ((3 - ((bit >> 3) & 0x3)) + 4*(bit >> 5)) argument
16 #define BIT_INDEX(bit) (bit >> 3) argument
18 #define BIT_VAL(bit) (1 << (bit & 0x7)) argument
38 unsigned int bit; in test_bitfield() local
43 for (bit = 0U; bit < 32; ++bit) { in test_bitfield()
44 sys_set_bit((mem_addr_t)&b1, bit); in test_bitfield()
46 zassert_equal(b1, (1 << bit), in test_bitfield()
47 "sys_set_bit failed on bit %d\n", bit); in test_bitfield()
49 zassert_true(sys_test_bit((mem_addr_t)&b1, bit), in test_bitfield()
50 "sys_test_bit did not detect bit %d\n", bit); in test_bitfield()
[all …]
Dbitarray.c16 #define BIT_INDEX(bit) ((3 - ((bit >> 3) & 0x3)) + 4*(bit >> 5)) argument
18 #define BIT_INDEX(bit) (bit >> 3) argument
20 #define BIT_VAL(bit) (1 << (bit & 0x7)) argument
131 size_t bit, bundle_idx, bit_idx_in_bundle; in test_bitarray_set_clear() local
140 for (bit = 0U; bit < ba.num_bits; ++bit) { in test_bitarray_set_clear()
141 bundle_idx = bit / (sizeof(ba.bundles[0]) * 8); in test_bitarray_set_clear()
142 bit_idx_in_bundle = bit % (sizeof(ba.bundles[0]) * 8); in test_bitarray_set_clear()
144 ret = sys_bitarray_set_bit(&ba, bit); in test_bitarray_set_clear()
146 "sys_bitarray_set_bit failed on bit %d", bit); in test_bitarray_set_clear()
148 "sys_bitarray_set_bit did not set bit %d\n", bit); in test_bitarray_set_clear()
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/Zephyr-Core-2.7.6/include/arch/common/
Dsys_bitops.h24 static ALWAYS_INLINE void sys_set_bit(mem_addr_t addr, unsigned int bit) in sys_set_bit() argument
28 *(volatile uint32_t *)addr = temp | (1 << bit); in sys_set_bit()
31 static ALWAYS_INLINE void sys_clear_bit(mem_addr_t addr, unsigned int bit) in sys_clear_bit() argument
35 *(volatile uint32_t *)addr = temp & ~(1 << bit); in sys_clear_bit()
38 static ALWAYS_INLINE int sys_test_bit(mem_addr_t addr, unsigned int bit) in sys_test_bit() argument
42 return temp & (1 << bit); in sys_test_bit()
46 void sys_bitfield_set_bit(mem_addr_t addr, unsigned int bit) in sys_bitfield_set_bit() argument
51 sys_set_bit(addr + ((bit >> 5) << 2), bit & 0x1F); in sys_bitfield_set_bit()
55 void sys_bitfield_clear_bit(mem_addr_t addr, unsigned int bit) in sys_bitfield_clear_bit() argument
57 sys_clear_bit(addr + ((bit >> 5) << 2), bit & 0x1F); in sys_bitfield_clear_bit()
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Dffs.h63 int bit; in find_lsb_set()
69 for (bit = 0; bit < 32; bit++) { in find_lsb_set()
70 if ((op & (1 << bit)) != 0) { in find_lsb_set()
71 return (bit + 1); in find_lsb_set()
/Zephyr-Core-2.7.6/include/sys/
Datomic.h79 #define ATOMIC_MASK(bit) (1U << ((uint32_t)(bit) & (ATOMIC_BITS - 1U))) argument
80 #define ATOMIC_ELEM(addr, bit) ((addr) + ((bit) / ATOMIC_BITS)) argument
127 static inline bool atomic_test_bit(const atomic_t *target, int bit) in atomic_test_bit() argument
129 atomic_val_t val = atomic_get(ATOMIC_ELEM(target, bit)); in atomic_test_bit()
131 return (1 & (val >> (bit & (ATOMIC_BITS - 1)))) != 0; in atomic_test_bit()
145 static inline bool atomic_test_and_clear_bit(atomic_t *target, int bit) in atomic_test_and_clear_bit() argument
147 atomic_val_t mask = ATOMIC_MASK(bit); in atomic_test_and_clear_bit()
150 old = atomic_and(ATOMIC_ELEM(target, bit), ~mask); in atomic_test_and_clear_bit()
166 static inline bool atomic_test_and_set_bit(atomic_t *target, int bit) in atomic_test_and_set_bit() argument
168 atomic_val_t mask = ATOMIC_MASK(bit); in atomic_test_and_set_bit()
[all …]
Dbitarray.h65 int sys_bitarray_set_bit(sys_bitarray_t *bitarray, size_t bit);
77 int sys_bitarray_clear_bit(sys_bitarray_t *bitarray, size_t bit);
90 int sys_bitarray_test_bit(sys_bitarray_t *bitarray, size_t bit, int *val);
103 int sys_bitarray_test_and_set_bit(sys_bitarray_t *bitarray, size_t bit, int *prev_val);
116 int sys_bitarray_test_and_clear_bit(sys_bitarray_t *bitarray, size_t bit, int *prev_val);
/Zephyr-Core-2.7.6/include/arch/x86/ia32/
Dsys_io.h19 void sys_io_set_bit(io_port_t port, unsigned int bit) in sys_io_set_bit() argument
27 : "a" (reg), "Nd" (port), "Ir" (bit)); in sys_io_set_bit()
31 void sys_io_clear_bit(io_port_t port, unsigned int bit) in sys_io_clear_bit() argument
39 : "a" (reg), "Nd" (port), "Ir" (bit)); in sys_io_clear_bit()
43 int sys_io_test_bit(io_port_t port, unsigned int bit) in sys_io_test_bit() argument
50 : "Nd" (port), "Ir" (bit)); in sys_io_test_bit()
56 int sys_io_test_and_set_bit(io_port_t port, unsigned int bit) in sys_io_test_and_set_bit() argument
60 ret = sys_io_test_bit(port, bit); in sys_io_test_and_set_bit()
61 sys_io_set_bit(port, bit); in sys_io_test_and_set_bit()
67 int sys_io_test_and_clear_bit(io_port_t port, unsigned int bit) in sys_io_test_and_clear_bit() argument
[all …]
/Zephyr-Core-2.7.6/drivers/clock_control/
Dbeetle_clock_control.c32 uint8_t bit, enum arm_soc_state_t state) in beetle_set_clock() argument
40 base[0] |= (1 << bit); in beetle_set_clock()
43 base[2] |= (1 << bit); in beetle_set_clock()
46 base[4] |= (1 << bit); in beetle_set_clock()
55 static inline void beetle_ahb_set_clock_on(uint8_t bit, in beetle_ahb_set_clock_on() argument
59 bit, state); in beetle_ahb_set_clock_on()
62 static inline void beetle_ahb_set_clock_off(uint8_t bit, in beetle_ahb_set_clock_off() argument
66 bit, state); in beetle_ahb_set_clock_off()
69 static inline void beetle_apb_set_clock_on(uint8_t bit, in beetle_apb_set_clock_on() argument
73 bit, state); in beetle_apb_set_clock_on()
[all …]
/Zephyr-Core-2.7.6/include/arch/arc/v2/
Dsys_io.h62 void sys_io_set_bit(io_port_t port, unsigned int bit) in sys_io_set_bit() argument
71 "r" (reg), "ir" (bit) in sys_io_set_bit()
76 void sys_io_clear_bit(io_port_t port, unsigned int bit) in sys_io_clear_bit() argument
85 "r" (reg), "ir" (bit) in sys_io_clear_bit()
90 int sys_io_test_bit(io_port_t port, unsigned int bit) in sys_io_test_bit() argument
101 "r" (reg), "ir" (bit), "i" (status) in sys_io_test_bit()
108 int sys_io_test_and_set_bit(io_port_t port, unsigned int bit) in sys_io_test_and_set_bit() argument
112 ret = sys_io_test_bit(port, bit); in sys_io_test_and_set_bit()
113 sys_io_set_bit(port, bit); in sys_io_test_and_set_bit()
119 int sys_io_test_and_clear_bit(io_port_t port, unsigned int bit) in sys_io_test_and_clear_bit() argument
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/Zephyr-Core-2.7.6/soc/arm/atmel_sam0/common/
Dsoc_samd2x.c22 NVMCTRL->CTRLB.bit.RWS = NVMCTRL_CTRLB_RWS_HALF_Val; in flash_waitstates_init()
39 while (GCLK->STATUS.bit.SYNCBUSY) { in wait_gclk_synchronization()
49 SYSCTRL->XOSC32K.bit.ENABLE = 1; in xosc32k_init()
51 while (!SYSCTRL->PCLKSR.bit.XOSC32KRDY) { in xosc32k_init()
71 while (!SYSCTRL->PCLKSR.bit.OSC32KRDY) { in osc32k_init()
102 while (!SYSCTRL->PCLKSR.bit.DFLLRDY) { in dfll_init()
112 while (!SYSCTRL->PCLKSR.bit.DFLLRDY) { in dfll_init()
120 while (!SYSCTRL->PCLKSR.bit.DFLLRDY) { in dfll_init()
124 SYSCTRL->DFLLCTRL.bit.ENABLE = 1; in dfll_init()
126 while (!SYSCTRL->PCLKSR.bit.DFLLLCKC || !SYSCTRL->PCLKSR.bit.DFLLLCKF) { in dfll_init()
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Dsoc_samd5x.c29 while (!OSC32KCTRL->STATUS.bit.XOSC32KRDY) { in osc32k_init()
52 OSCCTRL->Dpll[n].DPLLCTRLA.bit.ENABLE = 0; in dpll_init()
73 while (!(OSCCTRL->Dpll[n].DPLLSTATUS.bit.CLKRDY && in dpll_init()
74 OSCCTRL->Dpll[n].DPLLSTATUS.bit.LOCK)) { in dpll_init()
90 while (!OSCCTRL->STATUS.bit.DFLLRDY) { in dfll_init()
96 GCLK->CTRLA.bit.SWRST = 1; in gclk_reset()
97 while (GCLK->SYNCBUSY.bit.SWRST) { in gclk_reset()
126 CMCC->CTRL.bit.CEN = 1; in atmel_samd_init()
Dsoc_port.c24 pg->PMUX[idx].bit.PMUXO = func; in soc_port_pinmux_set()
26 pg->PMUX[idx].bit.PMUXE = func; in soc_port_pinmux_set()
28 pg->PINCFG[pin].bit.PMUXEN = 1; in soc_port_pinmux_set()
55 pincfg.bit.PULLEN = 1; in soc_port_configure()
59 pincfg.bit.INEN = 1; in soc_port_configure()
67 pincfg.bit.DRVSTR = 1; in soc_port_configure()
/Zephyr-Core-2.7.6/drivers/usb/device/
Dusb_dc_sam0.c171 regs->PADCAL.bit.TRANSN = pad_transn; in usb_sam0_load_padcal()
186 regs->PADCAL.bit.TRANSP = pad_transp; in usb_sam0_load_padcal()
201 regs->PADCAL.bit.TRIM = pad_trim; in usb_sam0_load_padcal()
220 MCLK->APBBMASK.bit.USB_ = 1; in usb_dc_attach()
230 PM->APBBMASK.bit.USB_ = 1; in usb_dc_attach()
236 while (GCLK->STATUS.bit.SYNCBUSY) { in usb_dc_attach()
241 regs->CTRLA.bit.SWRST = 1; in usb_dc_attach()
247 regs->QOSCTRL.bit.CQOS = 2; in usb_dc_attach()
248 regs->QOSCTRL.bit.DQOS = 2; in usb_dc_attach()
275 regs->CTRLA.bit.ENABLE = 1; in usb_dc_attach()
[all …]
/Zephyr-Core-2.7.6/lib/gui/lvgl/
Dlvgl_display_mono.c42 uint8_t bit; in lvgl_set_px_cb_mono() local
51 bit = 7 - y%8; in lvgl_set_px_cb_mono()
53 bit = y%8; in lvgl_set_px_cb_mono()
59 bit = 7 - x%8; in lvgl_set_px_cb_mono()
61 bit = x%8; in lvgl_set_px_cb_mono()
67 *buf_xy &= ~BIT(bit); in lvgl_set_px_cb_mono()
69 *buf_xy |= BIT(bit); in lvgl_set_px_cb_mono()
73 *buf_xy |= BIT(bit); in lvgl_set_px_cb_mono()
75 *buf_xy &= ~BIT(bit); in lvgl_set_px_cb_mono()
/Zephyr-Core-2.7.6/soc/arm/nuvoton_npcx/common/
Dsoc_dt.h62 .bit = DT_PHA(DT_DRV_INST(inst), clocks, bit), \
76 .bit = DT_CLOCKS_CELL_BY_IDX(DT_DRV_INST(inst), i, bit), \
134 .bit = DT_PHA(DT_INST_PINCTRL_0(inst, i), alts, bit), \
220 .bit = DT_PHA(NPCX_DT_IO_PHANDLE_FROM_PINCTRL(io_comp, inst, i), \
221 alts, bit), \
302 .bit = DT_PHA(NPCX_DT_PHANDLE_FROM_WUI_NAME(inst, name), miwus, \
303 bit), \
329 .bit = DT_PHA(NPCX_DT_PHANDLE_FROM_WUI_MAPS(inst, i), miwus, bit), \
449 .bit = DT_PHA(NPCX_DT_PHANDLE_VW_WUI(name), miwus, bit), \
529 .bit = DT_PHA(NPCX_DT_PHANDLE_FROM_LVOL_IO_PADS(i), \
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/Zephyr-Core-2.7.6/drivers/watchdog/
Dwdt_sam0.c31 #define WDT_SYNCBUSY WDT_REGS->STATUS.bit.SYNCBUSY
53 WDT_REGS->CTRLA.bit.ENABLE = on; in wdt_sam0_set_enable()
55 WDT_REGS->CTRL.bit.ENABLE = on; in wdt_sam0_set_enable()
62 return WDT_REGS->CTRLA.bit.ENABLE; in wdt_sam0_is_enabled()
64 return WDT_REGS->CTRL.bit.ENABLE; in wdt_sam0_is_enabled()
180 WDT_REGS->CTRLA.bit.WEN = 1; in wdt_sam0_install_timeout()
182 WDT_REGS->CTRL.bit.WEN = 1; in wdt_sam0_install_timeout()
192 WDT_REGS->EWCTRL.bit.EWOFFSET = per - 1U; in wdt_sam0_install_timeout()
196 WDT_REGS->CTRLA.bit.WEN = 0; in wdt_sam0_install_timeout()
198 WDT_REGS->CTRL.bit.WEN = 0; in wdt_sam0_install_timeout()
[all …]
/Zephyr-Core-2.7.6/include/arch/x86/
Darch.h155 static ALWAYS_INLINE void sys_set_bit(mem_addr_t addr, unsigned int bit) in sys_set_bit() argument
159 : "Ir" (bit) in sys_set_bit()
163 static ALWAYS_INLINE void sys_clear_bit(mem_addr_t addr, unsigned int bit) in sys_clear_bit() argument
167 : "Ir" (bit)); in sys_clear_bit()
170 static ALWAYS_INLINE int sys_test_bit(mem_addr_t addr, unsigned int bit) in sys_test_bit() argument
177 : "Ir" (bit)); in sys_test_bit()
183 unsigned int bit) in sys_test_and_set_bit() argument
190 : "Ir" (bit)); in sys_test_and_set_bit()
196 unsigned int bit) in sys_test_and_clear_bit() argument
203 : "Ir" (bit)); in sys_test_and_clear_bit()
/Zephyr-Core-2.7.6/drivers/dac/
Ddac_sam0.c76 regs->CTRLA.bit.SWRST = 1; in dac_sam0_init()
77 while (regs->STATUS.bit.SYNCBUSY) { in dac_sam0_init()
80 regs->CTRLB.bit.REFSEL = cfg->refsel; in dac_sam0_init()
81 regs->CTRLB.bit.EOEN = 1; in dac_sam0_init()
84 regs->CTRLA.bit.ENABLE = 1; in dac_sam0_init()
85 while (regs->STATUS.bit.SYNCBUSY) { in dac_sam0_init()
103 .pm_apbc_bit = DT_INST_CLOCKS_CELL_BY_NAME(n, pm, bit), \
/Zephyr-Core-2.7.6/drivers/dma/
Ddma_sam0.c127 DMA_REGS->CHCTRLB.bit.LVL = config->channel_priority; in dma_sam0_config()
165 chcfg->CHPRILVL.bit.PRILVL = config->channel_priority; in dma_sam0_config()
202 btctrl.bit.BEATSIZE = DMAC_BTCTRL_BEATSIZE_BYTE_Val; in dma_sam0_config()
205 btctrl.bit.BEATSIZE = DMAC_BTCTRL_BEATSIZE_HWORD_Val; in dma_sam0_config()
208 btctrl.bit.BEATSIZE = DMAC_BTCTRL_BEATSIZE_WORD_Val; in dma_sam0_config()
223 btctrl.bit.SRCINC = 1; in dma_sam0_config()
236 btctrl.bit.DSTINC = 1; in dma_sam0_config()
246 btctrl.bit.VALID = 1; in dma_sam0_config()
277 if (DMA_REGS->CHCTRLB.bit.TRIGSRC == 0) { in dma_sam0_start()
285 chcfg->CHCTRLA.bit.ENABLE = 1; in dma_sam0_start()
[all …]
/Zephyr-Core-2.7.6/lib/os/
Dbitarray.c218 int sys_bitarray_set_bit(sys_bitarray_t *bitarray, size_t bit) in sys_bitarray_set_bit() argument
228 if (bit >= bitarray->num_bits) { in sys_bitarray_set_bit()
233 idx = bit / bundle_bitness(bitarray); in sys_bitarray_set_bit()
234 off = bit % bundle_bitness(bitarray); in sys_bitarray_set_bit()
245 int sys_bitarray_clear_bit(sys_bitarray_t *bitarray, size_t bit) in sys_bitarray_clear_bit() argument
255 if (bit >= bitarray->num_bits) { in sys_bitarray_clear_bit()
260 idx = bit / bundle_bitness(bitarray); in sys_bitarray_clear_bit()
261 off = bit % bundle_bitness(bitarray); in sys_bitarray_clear_bit()
272 int sys_bitarray_test_bit(sys_bitarray_t *bitarray, size_t bit, int *val) in sys_bitarray_test_bit() argument
287 if (bit >= bitarray->num_bits) { in sys_bitarray_test_bit()
[all …]
/Zephyr-Core-2.7.6/drivers/interrupt_controller/
Dintc_miwu.c102 && cb->params.wui.bit == wui_bit) { in intc_miwu_dispatch_gpio_isr()
124 && cb->wui.bit == wui_bit) { in intc_miwu_dispatch_generic_isr()
163 NPCX_WKEN(base, wui->group) |= BIT(wui->bit); in npcx_miwu_irq_enable()
170 NPCX_WKEN(base, wui->group) &= ~BIT(wui->bit); in npcx_miwu_irq_disable()
177 NPCX_WKINEN(base, wui->group) |= BIT(wui->bit); in npcx_miwu_io_enable()
184 NPCX_WKINEN(base, wui->group) &= ~BIT(wui->bit); in npcx_miwu_io_disable()
191 return IS_BIT_SET(NPCX_WKEN(base, wui->group), wui->bit); in npcx_miwu_irq_get_state()
197 bool pending = IS_BIT_SET(NPCX_WKPND(base, wui->group), wui->bit); in npcx_miwu_irq_get_and_clear_pending()
200 NPCX_WKPCL(base, wui->group) = BIT(wui->bit); in npcx_miwu_irq_get_and_clear_pending()
210 uint8_t pmask = BIT(wui->bit); in npcx_miwu_interrupt_configure()
[all …]
/Zephyr-Core-2.7.6/drivers/gpio/
Dgpio_nrfx.c335 uint32_t bit = 1U << pin; in cfg_edge_sense_pins() local
341 if (edge_pins & bit) { in cfg_edge_sense_pins()
343 uint32_t sense = (sense_levels & bit) ? in cfg_edge_sense_pins()
348 edge_pins &= ~bit; in cfg_edge_sense_pins()
351 bit <<= 1; in cfg_edge_sense_pins()
379 uint32_t bit = 1U << pin; in cfg_level_pins() local
384 if (level_pins & bit) { in cfg_level_pins()
389 level_pins &= ~bit; in cfg_level_pins()
392 bit <<= 1; in cfg_level_pins()
423 uint32_t bit = 1U << pin; in check_level_trigger_pins() local
[all …]
/Zephyr-Core-2.7.6/arch/arm64/core/
DKconfig22 This option signifies the use of a CPU of the Cortex-R 64-bit family.
112 The Armv8-A architecture introduces the ability to use 64-bit and
113 32-bit Execution states, known as AArch64 and AArch32 respectively.
115 addresses in 64-bit registers and allows instructions in the base
116 instruction set to use 64-bit registers for their processing. The AArch32
117 Execution state is a 32-bit Execution state that preserves backwards
189 bool "32-bit"
192 bool "36-bit"
195 bool "40-bit"
198 bool "42-bit"
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/Zephyr-Core-2.7.6/boards/posix/native_posix/
DKconfig.board4 bool "Native POSIX for 32-bit host"
9 as a 32-bit executable.
15 bool "Native POSIX for 64-bit host"
21 as a 64-bit executable.
/Zephyr-Core-2.7.6/drivers/spi/
Dspi_sam0.c87 ctrla.bit.MODE = SERCOM_SPI_CTRLA_MODE_SPI_MASTER_Val; in spi_sam0_configure()
90 ctrla.bit.DORD = 1; in spi_sam0_configure()
94 ctrla.bit.CPOL = 1; in spi_sam0_configure()
98 ctrla.bit.CPHA = 1; in spi_sam0_configure()
105 ctrla.bit.DOPO = 0; in spi_sam0_configure()
106 ctrla.bit.DIPO = 0; in spi_sam0_configure()
109 ctrla.bit.ENABLE = 1; in spi_sam0_configure()
110 ctrlb.bit.RXEN = 1; in spi_sam0_configure()
117 ctrlb.bit.CHSIZE = 0; in spi_sam0_configure()
126 regs->CTRLA.bit.ENABLE = 0; in spi_sam0_configure()
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