Lines Matching refs:bit
87 ctrla.bit.MODE = SERCOM_SPI_CTRLA_MODE_SPI_MASTER_Val; in spi_sam0_configure()
90 ctrla.bit.DORD = 1; in spi_sam0_configure()
94 ctrla.bit.CPOL = 1; in spi_sam0_configure()
98 ctrla.bit.CPHA = 1; in spi_sam0_configure()
105 ctrla.bit.DOPO = 0; in spi_sam0_configure()
106 ctrla.bit.DIPO = 0; in spi_sam0_configure()
109 ctrla.bit.ENABLE = 1; in spi_sam0_configure()
110 ctrlb.bit.RXEN = 1; in spi_sam0_configure()
117 ctrlb.bit.CHSIZE = 0; in spi_sam0_configure()
126 regs->CTRLA.bit.ENABLE = 0; in spi_sam0_configure()
159 while (!regs->INTFLAG.bit.DRE) { in spi_sam0_shift_master()
165 while (!regs->INTFLAG.bit.RXC) { in spi_sam0_shift_master()
179 while (!regs->INTFLAG.bit.TXC) { in spi_sam0_finish()
182 while (regs->INTFLAG.bit.RXC) { in spi_sam0_finish()
197 while (!regs->INTFLAG.bit.DRE) { in spi_sam0_fast_tx()
226 while (!regs->INTFLAG.bit.DRE) { in spi_sam0_fast_rx()
235 while (!regs->INTFLAG.bit.RXC) { in spi_sam0_fast_rx()
242 while (!regs->INTFLAG.bit.RXC) { in spi_sam0_fast_rx()
282 while (!regs->INTFLAG.bit.RXC) { in spi_sam0_fast_txrx()
292 while (!regs->INTFLAG.bit.RXC) { in spi_sam0_fast_txrx()
746 .mclk_mask = BIT(DT_INST_CLOCKS_CELL_BY_NAME(n, mclk, bit)), \
754 .pm_apbcmask = BIT(DT_INST_CLOCKS_CELL_BY_NAME(n, pm, bit)), \