| /Zephyr-latest/samples/drivers/counter/alarm/src/ |
| D | main.c | 19 #define TIMER DT_NODELABEL(tc4) macro
21 #define TIMER DT_NODELABEL(tc0) macro
23 #define TIMER DT_NODELABEL(extrtc0) macro
25 #define TIMER DT_NODELABEL(rtc0) macro
27 #define TIMER DT_CHOSEN(counter) macro
29 #define TIMER DT_INST(0, st_stm32_counter) macro
31 #define TIMER DT_INST(0, st_stm32_rtc) macro
33 #define TIMER DT_NODELABEL(timer3) macro
35 #define TIMER DT_NODELABEL(counter0) macro
37 #define TIMER DT_INST(0, xlnx_xps_timer_1_00_a) macro
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| /Zephyr-latest/boards/qemu/cortex_m0/ |
| D | nrf_timer_timer.c | 18 #define TIMER NRF_TIMER0 macro
38 nrf_timer_cc_set(TIMER, NRF_TIMER_CC_CHANNEL0, cyc & COUNTER_MAX); in set_comparator()
43 return nrf_timer_cc_get(TIMER, NRF_TIMER_CC_CHANNEL0); in get_comparator()
48 nrf_timer_event_clear(TIMER, NRF_TIMER_EVENT_COMPARE0); in event_clear()
53 nrf_timer_int_disable(TIMER, NRF_TIMER_INT_COMPARE0_MASK); in int_disable()
58 nrf_timer_int_enable(TIMER, NRF_TIMER_INT_COMPARE0_MASK); in int_enable()
63 nrf_timer_task_trigger(TIMER, in counter()
66 return nrf_timer_cc_get(TIMER, NRF_TIMER_CC_CHANNEL1); in counter()
238 nrf_timer_prescaler_set(TIMER, NRF_TIMER_FREQ_1MHz); in sys_clock_driver_init()
239 nrf_timer_bit_width_set(TIMER, NRF_TIMER_BIT_WIDTH_32); in sys_clock_driver_init()
[all …]
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| /Zephyr-latest/drivers/counter/ |
| D | counter_max32_timer.c | 307 #define TIMER(_num) DT_INST_PARENT(_num) macro
308 #define MAX32_TIM(idx) ((mxc_tmr_regs_t *)DT_REG_ADDR(TIMER(idx)))
314 IRQ_CONNECT(DT_IRQN(TIMER(_num)), DT_IRQ(TIMER(_num), priority), \
316 irq_enable(DT_IRQN(TIMER(_num))); \
325 DT_PROP(TIMER(_num), clock_source)) / \
326 DT_PROP(TIMER(_num), prescaler), \
330 .regs = (mxc_tmr_regs_t *)DT_REG_ADDR(TIMER(_num)), \
331 .clock = DEVICE_DT_GET(DT_CLOCKS_CTLR(TIMER(_num))), \
332 .perclk.bus = DT_CLOCKS_CELL(TIMER(_num), offset), \
333 .perclk.bit = DT_CLOCKS_CELL(TIMER(_num), bit), \
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| D | counter_renesas_ra_agt.c | 536 #define TIMER(idx) DT_INST_PARENT(idx) macro
555 .source_div = DT_PROP(TIMER(n), renesas_prescaler), \
556 .count_source = DT_STRING_TOKEN(TIMER(n), renesas_count_source), \
557 .channel = DT_PROP(TIMER(n), channel), \
558 .channel_irq = DT_IRQ_BY_NAME(TIMER(n), agtcmai, irq), \
559 .channel_ipl = DT_IRQ_BY_NAME(TIMER(n), agtcmai, priority), \
560 .cycle_end_irq = DT_IRQ_BY_NAME(TIMER(n), agti, irq), \
561 .cycle_end_ipl = DT_IRQ_BY_NAME(TIMER(n), agti, priority), \
562 .resolution = DT_PROP(TIMER(n), renesas_resolution), \
563 .dt_reg = DT_REG_ADDR(TIMER(n)), \
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| D | counter_ll_stm32_timer.c | 627 #define TIMER(idx) DT_INST_PARENT(idx) macro
630 #define TIM(idx) ((TIM_TypeDef *)DT_REG_ADDR(TIMER(idx)))
633 BUILD_ASSERT(DT_PROP(TIMER(idx), st_prescaler) <= 0xFFFF, \
643 IRQ_CONNECT(DT_IRQN(TIMER(idx)), \
644 DT_IRQ(TIMER(idx), priority), \
648 irq_enable(DT_IRQN(TIMER(idx))); \
661 .prescaler = DT_PROP(TIMER(idx), st_prescaler), \
663 .bus = DT_CLOCKS_CELL(TIMER(idx), bus), \
664 .enr = DT_CLOCKS_CELL(TIMER(idx), bits) \
667 .irqn = DT_IRQN(TIMER(idx)), \
[all …]
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| D | counter_smartbond_timer.c | 99 case (uint32_t)TIMER: in counter_smartbond_pdc_trigger_get()
213 volatile uint32_t *timer_clear_irq_reg = ((TIMER_Type *)timer) == TIMER ? in counter_smartbond_set_alarm()
333 TIMER_Type *timer0 = ((TIMER_Type *)cfg->timer) == TIMER ? TIMER : NULL; in counter_smartbond_init_timer()
477 __IOM uint32_t *timer_clear_irq_reg = ((TIMER_Type *)timer) == TIMER ? in counter_smartbond_irq_handler()
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| D | counter_nxp_mrt.c | 106 *ticks = base->CHANNEL[channel_id].TIMER & MRT_CHANNEL_TIMER_VALUE_MASK; in nxp_mrt_get_value()
121 uint32_t current_val = base->CHANNEL[channel_id].TIMER & MRT_CHANNEL_TIMER_VALUE_MASK; in nxp_mrt_set_top_value()
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| /Zephyr-latest/soc/mediatek/mt8xxx/ |
| D | cpuclk.c | 77 #define TIMER (((volatile uint32_t *)DT_REG_ADDR(DT_NODELABEL(ostimer64)))[3]) macro
80 uint32_t t0 = TIMER; in delay_us()
82 while (TIMER - t0 < (us * 13)) { in delay_us()
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| /Zephyr-latest/boards/adi/sdp_k1/ |
| D | adi_sdp_120pin_connector.dtsi | 30 /* TIMER A */
36 /* TIMER D */
39 /* TIMER B */
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| /Zephyr-latest/boards/qemu/cortex_m0/doc/ |
| D | index.rst | 12 * TIMER (nRF TIMER System Clock)
34 | nRF TIMER | on-chip | system clock |
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| /Zephyr-latest/modules/hal_rpi_pico/ |
| D | Kconfig | 51 Use the TIMER driver from pico-sdk
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| /Zephyr-latest/boards/qemu/kvm_arm64/doc/ |
| D | index.rst | 30 | ARM TIMER | on-chip | system clock |
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| /Zephyr-latest/drivers/display/ |
| D | Kconfig.nrf_led_matrix | 17 The driver uses one TIMER instance and, depending on what is set in
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| /Zephyr-latest/samples/subsys/usb/uac2_explicit_feedback/ |
| D | README.rst | 40 with the use of DPPI, TIMER and GPIOTE input. Alternatively, if the GPIOTE input
41 is not available, the DPPI and TIMER peripherals on nRF5340 can be configured to
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| /Zephyr-latest/modules/hal_ambiq/ |
| D | Kconfig | 31 Use the TIMER driver from Ambiq HAL
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| /Zephyr-latest/modules/hal_infineon/ |
| D | Kconfig | 74 Enable WATCHDOG TIMER (WDT) HAL module
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| /Zephyr-latest/boards/khadas/edgev/doc/ |
| D | index.rst | 24 | ARM TIMER | on-chip | System Clock |
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| /Zephyr-latest/boards/intel/socfpga/agilex_socdk/doc/ |
| D | index.rst | 36 | ARM TIMER | on-chip | System Clock |
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| /Zephyr-latest/boards/wch/ch32v003evt/doc/ |
| D | index.rst | 38 | TIMER | on-chip | timer |
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| /Zephyr-latest/modules/hal_nordic/nrfx/ |
| D | Kconfig.logging | 120 bool "TIMER driver logging"
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| /Zephyr-latest/boards/intel/socfpga/agilex5_socdk/doc/ |
| D | index.rst | 38 | ARM TIMER | on-chip | ARM system timer |
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| /Zephyr-latest/boards/qemu/cortex_a53/doc/ |
| D | index.rst | 30 | ARM TIMER | on-chip | system clock |
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| /Zephyr-latest/boards/arm/fvp_base_revc_2xaemv8a/doc/ |
| D | index.rst | 34 | ARM GENERIC TIMER | on-chip | system clock |
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| /Zephyr-latest/drivers/serial/ |
| D | Kconfig.nrfx | 45 and hardware assisted required TIMER peripheral instance and PPI channel
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| /Zephyr-latest/lib/posix/options/ |
| D | Kconfig.timer | 92 module = TIMER
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