Home
last modified time | relevance | path

Searched refs:STM32_SYSCLK_SRC_PLL (Results 1 – 12 of 12) sorted by relevance

/Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32wba_core/src/
Dtest_stm32_clock_configuration.c29 #if STM32_SYSCLK_SRC_PLL in ZTEST()
43 zassert_true((STM32_SYSCLK_SRC_PLL || in ZTEST()
/Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32u5_core/src/
Dtest_stm32_clock_configuration.c29 #if STM32_SYSCLK_SRC_PLL in ZTEST()
47 zassert_true((STM32_SYSCLK_SRC_PLL || in ZTEST()
/Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32h5_core/src/
Dtest_stm32_clock_configuration.c29 #if STM32_SYSCLK_SRC_PLL in ZTEST()
47 zassert_true((STM32_SYSCLK_SRC_PLL || in ZTEST()
/Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32h7_core/src/
Dtest_stm32_clock_configuration.c29 #if STM32_SYSCLK_SRC_PLL in ZTEST()
47 zassert_true((STM32_SYSCLK_SRC_PLL || in ZTEST()
/Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_core/src/
Dtest_stm32_clock_configuration.c38 #if STM32_SYSCLK_SRC_PLL in ZTEST()
56 zassert_true((STM32_SYSCLK_SRC_PLL || in ZTEST()
/Zephyr-latest/drivers/clock_control/
Dclock_stm32_ll_wba.c184 if (IS_ENABLED(STM32_SYSCLK_SRC_PLL)) { in stm32_clock_control_get_subsys_rate()
532 if (IS_ENABLED(STM32_SYSCLK_SRC_PLL) && in stm32_clock_control_init()
553 if (IS_ENABLED(STM32_SYSCLK_SRC_PLL)) { in stm32_clock_control_init()
576 if (IS_ENABLED(STM32_SYSCLK_SRC_PLL)) { in stm32_clock_control_init()
588 if (IS_ENABLED(STM32_SYSCLK_SRC_PLL)) { in stm32_clock_control_init()
Dclock_stm32_ll_wb0.c740 #elif defined(STM32_SYSCLK_SRC_HSI) || defined(STM32_SYSCLK_SRC_PLL) in stm32_clock_control_init()
744 # if defined(STM32_SYSCLK_SRC_PLL) in stm32_clock_control_init()
Dclock_stm32_ll_h5.c100 #if defined(STM32_SYSCLK_SRC_PLL) in get_sysclk_frequency()
747 if (IS_ENABLED(STM32_SYSCLK_SRC_PLL)) { in stm32_clock_control_init()
Dclock_stm32_ll_common.c396 #if defined(STM32_SRC_PLLCLK) & defined(STM32_SYSCLK_SRC_PLL) in stm32_clock_control_get_subsys_rate()
840 #if STM32_SYSCLK_SRC_PLL in stm32_clock_control_init()
Dclock_stm32_ll_u5.c105 #if defined(STM32_SYSCLK_SRC_PLL) in get_sysclk_frequency()
880 if (IS_ENABLED(STM32_SYSCLK_SRC_PLL)) { in stm32_clock_control_init()
Dclock_stm32_ll_h7.c79 #if defined(STM32_SYSCLK_SRC_PLL)
1149 if (IS_ENABLED(STM32_SYSCLK_SRC_PLL)) {
/Zephyr-latest/include/zephyr/drivers/clock_control/
Dstm32_clock_control.h130 #define STM32_SYSCLK_SRC_PLL 1 macro