STM32_PLL_M_DIVISOR (reference) in projects: Zephyr-Core-2.7.6

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Searched refs:STM32_PLL_M_DIVISOR (Results 1 – 7 of 7) sorted by relevance

/Zephyr-Core-2.7.6/drivers/clock_control/
D	clock_stm32f2_f4_f7.c	`33 pllinit->PLLM = pllm(STM32_PLL_M_DIVISOR); in config_pll_init()`
D	clock_stm32g0.c	`35 pllinit->PLLM = pll_div(STM32_PLL_M_DIVISOR); in config_pll_init()`
D	clock_stm32g4.c	`33 pllinit->PLLM = pllm(STM32_PLL_M_DIVISOR); in config_pll_init()`
D	clock_stm32l4_l5_wb_wl.c	`34 pllinit->PLLM = pllm(STM32_PLL_M_DIVISOR); in config_pll_init()`
D	clock_stm32_ll_u5.c	`52 pllinit->PLLM = STM32_PLL_M_DIVISOR; in config_pll_init() 321 STM32_PLL_M_DIVISOR, in config_src_sysclk_pll() 337 tmp = MIN(tmp / STM32_PLL_M_DIVISOR / 8000000, 16); in config_src_sysclk_pll()`
D	clock_stm32_ll_h7.c	`76 STM32_PLL_M_DIVISOR,\ 610 r = get_vco_input_range(STM32_PLL_M_DIVISOR, &vco_input_range); in stm32_clock_control_init() 621 LL_RCC_PLL1_SetM(STM32_PLL_M_DIVISOR); in stm32_clock_control_init()`
/Zephyr-Core-2.7.6/include/drivers/clock_control/
D	stm32_clock_control.h	`174 #define STM32_PLL_M_DIVISOR DT_PROP(DT_NODELABEL(pll), div_m) macro 180 #define STM32_PLL_M_DIVISOR CONFIG_CLOCK_STM32_PLL_M_DIVISOR macro`

TraceRecorderSource-2.7.6
TraceRecorderSource-3.4.0
Zephyr-Core-2.7.6
Zephyr-Core-3.4.0
Zephyr-Core-3.5.0
Zephyr-Core-3.6.0
Zephyr-Core-3.7.0
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babblesim_ext_2G4_channel_multiatt-3.4.0
babblesim_ext_2G4_channel_multiatt-3.7.0-3.6.0-3.5.0
babblesim_ext_2G4_device_WLAN_actmod-3.7.0-3.6.0-3.5.0-3.4.0
babblesim_ext_2G4_device_burst_interferer-3.7.0-3.6.0-3.5.0-3.4.0
babblesim_ext_2G4_device_playback-3.6.0-3.5.0-3.4.0
babblesim_ext_2G4_device_playback-3.7.0
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babblesim_ext_2G4_libPhyComv1-3.7.0
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