Searched refs:MHZ (Results 1 – 25 of 32) sorted by relevance
12
| /Zephyr-Core-2.7.6/drivers/clock_control/ |
| D | clock_control_npcx.c | 145 BUILD_ASSERT(CORE_CLK <= MHZ(100) && CORE_CLK >= MHZ(4) &&
149 BUILD_ASSERT(CORE_CLK / (FIUDIV_VAL + 1) <= MHZ(50) &&
150 CORE_CLK / (FIUDIV_VAL + 1) >= MHZ(4),
152 BUILD_ASSERT(CORE_CLK / (AHB6DIV_VAL + 1) <= MHZ(50) &&
153 CORE_CLK / (AHB6DIV_VAL + 1) >= MHZ(4),
155 BUILD_ASSERT(APBSRC_CLK / (APB1DIV_VAL + 1) <= MHZ(50) &&
156 APBSRC_CLK / (APB1DIV_VAL + 1) >= MHZ(4) &&
159 BUILD_ASSERT(APBSRC_CLK / (APB2DIV_VAL + 1) <= MHZ(50) &&
160 APBSRC_CLK / (APB2DIV_VAL + 1) >= MHZ(8) &&
163 BUILD_ASSERT(APBSRC_CLK / (APB3DIV_VAL + 1) <= MHZ(50) &&
[all …]
|
| D | clock_control_esp32.c | 183 return MHZ(esp32_rom_g_ticks_per_us_pro); in esp_clk_cpu_freq()
188 return MHZ(MIN(esp32_rom_g_ticks_per_us_pro, 80)); in esp_clk_apb_freq()
202 uint32_t apb_freq = MHZ(freq); in esp32_cpu_freq_to_xtal()
207 REG_WRITE(APB_CTRL_XTAL_TICK_CONF_REG, MHZ(freq) / REF_CLK_FREQ - 1); in esp32_cpu_freq_to_xtal()
310 *rate = MHZ(80); in clock_control_esp32_get_rate()
374 MHZ(DT_PROP(DT_INST(0, cdns_tensilica_xtensa_lx6), clock_frequency)),
|
| D | clock_stm32_ll_h7.c | 333 if (MHZ(1) <= vco_freq && vco_freq <= MHZ(2)) { in get_vco_input_range()
335 } else if (MHZ(2) < vco_freq && vco_freq <= MHZ(4)) { in get_vco_input_range()
337 } else if (MHZ(4) < vco_freq && vco_freq <= MHZ(8)) { in get_vco_input_range()
339 } else if (MHZ(8) < vco_freq && vco_freq <= MHZ(16)) { in get_vco_input_range()
|
| D | clock_stm32g4.c | 38 if (sys_clock_hw_cycles_per_sec() >= MHZ(150)) { in config_pll_init()
|
| D | clock_stm32l4_l5_wb_wl.c | 39 if (sys_clock_hw_cycles_per_sec() >= MHZ(80)) { in config_pll_init()
|
| D | clock_control_mchp_xec.c | 562 *rate = MHZ(96); in xec_clock_control_get_subsys_rate()
566 *rate = MHZ(96) / pcr->PROC_CLK_CTRL; in xec_clock_control_get_subsys_rate()
570 *rate = MHZ(48); in xec_clock_control_get_subsys_rate()
575 *rate = MHZ(48) / temp; in xec_clock_control_get_subsys_rate()
|
| D | clock_stm32_ll_u5.c | 498 if (new_hclk_freq > MHZ(24)) { in config_src_sysclk_msis()
|
| /Zephyr-Core-2.7.6/soc/arm/nxp_kinetis/ke1xf/ |
| D | soc.c | 89 #if MHZ(2) == DT_PROP(SCG_CLOCK_NODE(sirc_clk), clock_frequency)
91 #elif MHZ(8) == DT_PROP(SCG_CLOCK_NODE(sirc_clk), clock_frequency)
107 #if MHZ(48) == DT_PROP(SCG_CLOCK_NODE(firc_clk), clock_frequency)
109 #elif MHZ(52) == DT_PROP(SCG_CLOCK_NODE(firc_clk), clock_frequency)
111 #elif MHZ(56) == DT_PROP(SCG_CLOCK_NODE(firc_clk), clock_frequency)
113 #elif MHZ(60) == DT_PROP(SCG_CLOCK_NODE(firc_clk), clock_frequency)
|
| /Zephyr-Core-2.7.6/soc/arm/microchip_mec/mec1701/ |
| D | soc.h | 10 #define SYSCLK_DEFAULT_IOSC_HZ MHZ(48)
|
| /Zephyr-Core-2.7.6/soc/arm/microchip_mec/mec1501/ |
| D | soc.h | 10 #define SYSCLK_DEFAULT_IOSC_HZ MHZ(48)
|
| /Zephyr-Core-2.7.6/soc/arc/snps_emsdp/ |
| D | soc.h | 20 #define SYSCLK_DEFAULT_IOSC_HZ MHZ(100)
|
| /Zephyr-Core-2.7.6/soc/arc/snps_arc_iot/ |
| D | soc.h | 20 #define SYSCLK_DEFAULT_IOSC_HZ MHZ(16)
|
| /Zephyr-Core-2.7.6/soc/arc/snps_emsk/ |
| D | soc.h | 21 #define SYSCLK_DEFAULT_IOSC_HZ MHZ(50)
|
| /Zephyr-Core-2.7.6/soc/arm/ti_lm3s6965/ |
| D | soc.h | 22 #define SYSCLK_DEFAULT_IOSC_HZ MHZ(12)
|
| /Zephyr-Core-2.7.6/drivers/timer/ |
| D | rv32m1_lptmr_timer.c | 32 (MHZ(8) != CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC)
|
| /Zephyr-Core-2.7.6/include/sys/ |
| D | util.h | 389 #define MHZ(x) (KHZ(x) * 1000) macro
|
| /Zephyr-Core-2.7.6/drivers/memc/ |
| D | memc_mcux_flexspi_hyperram.c | 159 .flexspiRootClk = MHZ(332), \
|
| /Zephyr-Core-2.7.6/drivers/i2c/ |
| D | i2c_mcux_flexcomm.c | 58 baudrate = MHZ(1); in mcux_flexcomm_configure()
|
| D | i2c_mcux.c | 67 baudrate = MHZ(1); in i2c_mcux_configure()
|
| D | i2c_gecko.c | 97 baudrate = MHZ(1); in i2c_gecko_configure()
|
| D | i2c_rv32m1_lpi2c.c | 66 baudrate = MHZ(1); in rv32m1_lpi2c_configure()
|
| D | i2c_mcux_lpi2c.c | 66 baudrate = MHZ(1); in mcux_lpi2c_configure()
|
| D | i2c_imx.c | 158 baudrate = MHZ(1); in i2c_imx_configure()
|
| /Zephyr-Core-2.7.6/drivers/pwm/ |
| D | pwm_ite_it8xxx2.c | 22 #define PWM_EC_FREQ MHZ(8)
|
| /Zephyr-Core-2.7.6/drivers/flash/ |
| D | flash_mcux_flexspi_nor.c | 529 .flexspiRootClk = MHZ(120), \
|
12
