1 /* 2 * Copyright (c) 2022 STMicroelectronics 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F7_CLOCK_H_ 7 #define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F7_CLOCK_H_ 8 9 #include "stm32_common_clocks.h" 10 11 /** Domain clocks */ 12 13 /** Bus clocks */ 14 #define STM32_CLOCK_BUS_AHB1 0x030 15 #define STM32_CLOCK_BUS_AHB2 0x034 16 #define STM32_CLOCK_BUS_AHB3 0x038 17 #define STM32_CLOCK_BUS_APB1 0x040 18 #define STM32_CLOCK_BUS_APB2 0x044 19 #define STM32_CLOCK_BUS_APB3 0x0A8 20 21 #define STM32_PERIPH_BUS_MIN STM32_CLOCK_BUS_AHB1 22 #define STM32_PERIPH_BUS_MAX STM32_CLOCK_BUS_APB3 23 24 /** Domain clocks */ 25 /* RM0386, 0390, 0402, 0430 § Dedicated Clock configuration register (RCC_DCKCFGRx) */ 26 27 /** System clock */ 28 /* defined in stm32_common_clocks.h */ 29 30 /** Fixed clocks */ 31 /* Low speed clocks defined in stm32_common_clocks.h */ 32 #define STM32_SRC_HSI (STM32_SRC_LSI + 1) 33 #define STM32_SRC_HSE (STM32_SRC_HSI + 1) 34 /** PLL clock outputs */ 35 #define STM32_SRC_PLL_P (STM32_SRC_HSE + 1) 36 #define STM32_SRC_PLL_Q (STM32_SRC_PLL_P + 1) 37 #define STM32_SRC_PLL_R (STM32_SRC_PLL_Q + 1) 38 /** Peripheral bus clock */ 39 #define STM32_SRC_PCLK (STM32_SRC_PLL_R + 1) 40 41 #define STM32_SRC_PLLI2S_R (STM32_SRC_PCLK + 1) 42 43 /** @brief RCC_CFGRx register offset */ 44 #define CFGR_REG 0x08 45 46 /** @brief RCC_BDCR register offset */ 47 #define BDCR_REG 0x70 48 49 /** @brief Device domain clocks selection helpers */ 50 /** CFGR devices */ 51 #define I2S_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 23, CFGR_REG) 52 #define MCO1_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x3, 21, CFGR_REG) 53 #define MCO1_PRE(val) STM32_DT_CLOCK_SELECT((val), 0x7, 24, CFGR_REG) 54 #define MCO2_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x3, 30, CFGR_REG) 55 #define MCO2_PRE(val) STM32_DT_CLOCK_SELECT((val), 0x7, 27, CFGR_REG) 56 57 /* MCO prescaler : division factor */ 58 #define MCO_PRE_DIV_1 0 59 #define MCO_PRE_DIV_2 4 60 #define MCO_PRE_DIV_3 5 61 #define MCO_PRE_DIV_4 6 62 #define MCO_PRE_DIV_5 7 63 64 /** BDCR devices */ 65 #define RTC_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 8, BDCR_REG) 66 67 /** @brief RCC_DKCFGR register offset */ 68 #define DCKCFGR1_REG 0x8C 69 #define DCKCFGR2_REG 0x90 70 71 /** @brief Dedicated clocks configuration register selection helpers */ 72 /** DKCFGR2 devices */ 73 #define USART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 0, DCKCFGR2_REG) 74 #define USART2_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 2, DCKCFGR2_REG) 75 #define USART3_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 4, DCKCFGR2_REG) 76 #define USART4_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 6, DCKCFGR2_REG) 77 #define USART5_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 8, DCKCFGR2_REG) 78 #define USART6_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 10, DCKCFGR2_REG) 79 #define USART7_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 12, DCKCFGR2_REG) 80 #define USART8_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 14, DCKCFGR2_REG) 81 #define I2C1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 16, DCKCFGR2_REG) 82 #define I2C2_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 18, DCKCFGR2_REG) 83 #define I2C3_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 20, DCKCFGR2_REG) 84 #define I2C4_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 22, DCKCFGR2_REG) 85 #define LPTIM1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 24, DCKCFGR2_REG) 86 #define CEC_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 26, DCKCFGR2_REG) 87 #define CK48M_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 27, DCKCFGR2_REG) 88 #define SDMMC1_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 28, DCKCFGR2_REG) 89 #define SDMMC2_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 29, DCKCFGR2_REG) 90 #define DSI_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 30, DCKCFGR2_REG) 91 92 #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F7_CLOCK_H_ */ 93
