1 /*
2  * Copyright (c) 2022 Linaro Limited
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  */
6 #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F1_CLOCK_H_
7 #define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F1_CLOCK_H_
8 
9 #include "stm32_common_clocks.h"
10 
11 /** Domain clocks */
12 
13 /** Bus clocks */
14 #define STM32_CLOCK_BUS_AHB1    0x014
15 #define STM32_CLOCK_BUS_APB2    0x018
16 #define STM32_CLOCK_BUS_APB1    0x01c
17 
18 #define STM32_PERIPH_BUS_MIN	STM32_CLOCK_BUS_AHB1
19 #define STM32_PERIPH_BUS_MAX	STM32_CLOCK_BUS_APB1
20 
21 /** System clock */
22 /* defined in stm32_common_clocks.h */
23 
24 /** Fixed clocks  */
25 /* Low speed clocks defined in stm32_common_clocks.h */
26 #define STM32_SRC_HSI           (STM32_SRC_LSI + 1)
27 #define STM32_SRC_HSE           (STM32_SRC_HSI + 1)
28 #define STM32_SRC_EXT_HSE       (STM32_SRC_HSE + 1)
29 #define STM32_SRC_PLLCLK        (STM32_SRC_EXT_HSE + 1)
30 
31 /** @brief RCC_CFGRx register offset */
32 #define CFGR1_REG               0x04
33 #define CFGR2_REG		0x2C
34 
35 /** @brief RCC_BDCR register offset */
36 #define BDCR_REG		0x20
37 
38 /** @brief Device domain clocks selection helpers */
39 /** CFGR2 devices */
40 #define I2S2_SEL(val)		STM32_DT_CLOCK_SELECT((val), 1, 17, CFGR2_REG)
41 #define I2S3_SEL(val)		STM32_DT_CLOCK_SELECT((val), 1, 18, CFGR2_REG)
42 /** BDCR devices */
43 #define RTC_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 8, BDCR_REG)
44 
45 /** CFGR1 devices */
46 #define MCO1_SEL(val)           STM32_DT_CLOCK_SELECT((val), 0x7, 24, CFGR1_REG)
47 /* No MCO prescaler support on STM32F1 series. */
48 
49 #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F1_CLOCK_H_ */
50