1 /* 2 * Copyright (c) 2022 Linaro Limited 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F0_CLOCK_H_ 7 #define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F0_CLOCK_H_ 8 9 #include "stm32_common_clocks.h" 10 11 /** Bus gatting clocks */ 12 #define STM32_CLOCK_BUS_AHB1 0x014 13 #define STM32_CLOCK_BUS_APB2 0x018 14 #define STM32_CLOCK_BUS_APB1 0x01c 15 16 #define STM32_PERIPH_BUS_MIN STM32_CLOCK_BUS_AHB1 17 #define STM32_PERIPH_BUS_MAX STM32_CLOCK_BUS_APB1 18 19 /** Domain clocks */ 20 21 /** System clock */ 22 /* defined in stm32_common_clocks.h */ 23 /** Fixed clocks */ 24 /* Low speed clocks defined in stm32_common_clocks.h */ 25 #define STM32_SRC_HSI (STM32_SRC_LSI + 1) 26 #define STM32_SRC_HSI14 (STM32_SRC_HSI + 1) 27 #define STM32_SRC_HSI48 (STM32_SRC_HSI14 + 1) 28 /** Bus clock */ 29 #define STM32_SRC_PCLK (STM32_SRC_HSI48 + 1) 30 /** PLL clock */ 31 #define STM32_SRC_PLLCLK (STM32_SRC_PCLK + 1) 32 33 /** @brief RCC_CFGRx register offset */ 34 #define CFGR1_REG 0x04 35 #define CFGR3_REG 0x30 36 37 /** @brief RCC_BDCR register offset */ 38 #define BDCR_REG 0x20 39 40 /** @brief Device domain clocks selection helpers */ 41 /** CFGR3 devices */ 42 #define USART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 0, CFGR3_REG) 43 #define I2C1_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 4, CFGR3_REG) 44 #define CEC_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 6, CFGR3_REG) 45 #define USB_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 7, CFGR3_REG) 46 #define USART2_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 16, CFGR3_REG) 47 #define USART3_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 18, CFGR3_REG) 48 /** BDCR devices */ 49 #define RTC_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 8, BDCR_REG) 50 51 /** CFGR1 devices */ 52 #define MCO1_SEL(val) STM32_DT_CLOCK_SELECT((val), 0xF, 24, CFGR1_REG) 53 #define MCO1_PRE(val) STM32_DT_CLOCK_SELECT((val), 0x7, 28, CFGR1_REG) 54 55 #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F0_CLOCK_H_ */ 56
